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| this is information on a product in full production. november 2014 docid022712 rev 7 1/141 1 M24LR64E-R dynamic nfc/rfid tag ic with 64-kbit eeprom, energy harvesting, i2c bus and iso 15693 rf interface datasheet - production data features i 2 c interface ? two-wire i 2 c serial interface supports 400 khz protocol ? single supply voltage: ? 1.8 v to 5.5 v ? byte and page write (up to 4 bytes) ? random and sequential read modes ? self-timed programming cycle ? automatic address incrementing ? enhanced esd/latch-up protection ? i2c timeout contactless interface ? iso 15693 and iso 18000-3 mode 1 compatible ? 13.56 mhz 7 khz carrier frequency ? to tag: 10% or 100% ask modulation using 1/4 (26 kbit/s) or 1/256 (1.6 kbit/s) pulse position coding ? from tag: load modulation using manchester coding with 423 khz and 484 khz subcarriers in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. supports the 53 kbit/s data rate with fast commands ? internal tuning capacitance: 27.5 pf ? 64-bit unique identifier (uid) ? read block & write (32-bit blocks) digital output pin ? user configurable pin: rf write in progress or rf busy mode energy harvesting ? analog pin for energy harvesting ? 4 sink current configurable ranges memory ? 64-kbit eeprom organized into: ? 8192 bytes in i 2 c mode ? 2048 blocks of 32 bits in rf mode ? write time ?i 2 c: 5 ms (max.) ? rf: 5.75 ms including the internal verify time ? more than 1 million write cycles ? more than 40-year data retention ? multiple password pr otection in rf mode ? single password protection in i 2 c mode ? package ?ecopack2 ? (rohs compliant and halogen-free) so8 (mn) 150 mils width ufdfpn8 (mc) 2 x 3 mm tssop8 (dw) sawn wafer on uv tape www.st.com
contents M24LR64E-R 2/141 docid022712 rev 7 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 rf write in progress / rf busy (rf wip/busy) . . . . . . . . . . . . . . . . . . . 15 2.4 energy harvesting analog output (vout) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 antenna coil (ac0, ac1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.1 device reset in rf mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.3 device reset in i2c mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 user memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 system memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 M24LR64E-R block security in rf mode . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 example of the M24LR64E-R security protection in rf mode . . . . . . . 26 4.2 M24LR64E-R block security in i2c mode (i2c_write_lock bit area) . . . . 27 4.3 configuration byte and control register . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 rf wip/busy pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.2 energy harvesting configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.3 field_on indicator bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.4 configuration byte access in i2c and rf modes . . . . . . . . . . . . . . . . . . 30 4.3.5 control register access in i2c or rf mode . . . . . . . . . . . . . . . . . . . . . . 30 4.4 iso 15693 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5i 2 c device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 docid022712 rev 7 3/141 M24LR64E-R contents 5.3 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 i2c timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5.1 i2c timeout on start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5.2 i2c timeout on clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.8 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.9 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.10 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 36 5.11 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.12 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.13 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.14 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.15 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.16 M24LR64E-R i 2 c password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.16.1 i 2 c present password command description . . . . . . . . . . . . . . . . . . . . . 39 5.16.2 i 2 c write password command description . . . . . . . . . . . . . . . . . . . . . . . 40 6 M24LR64E-R memory initial stat e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7 rf device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 rf communication and energy harvesting . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3 initial dialog for vicinity cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3.1 power transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3.2 frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3.3 operating field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 communication signal from vcd to M24LR64E-R . . . . . . . . . . . . . . . . 45 9 data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1 data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2 data coding mode: 1 out of 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3 vcd to M24LR64E-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 contents M24LR64E-R 4/141 docid022712 rev 7 9.4 start of frame (sof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 communication signal from M24LR64E-R to vcd . . . . . . . . . . . . . . . . 52 10.1 load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.2 subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.3 data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11 bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1 bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1.1 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1.2 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2 bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2.1 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2.2 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12 M24LR64E-R to vcd frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1 sof when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1.1 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1.2 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2 sof when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.2.1 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.2.2 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.3 eof when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.3.1 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.3.2 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.4 eof when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.4.1 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.4.2 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13 unique identifier (uid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14 application family identifier (afi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 15 data storage format identifier (dsfid) . . . . . . . . . . . . . . . . . . . . . . . . . 62 15.1 crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 16 M24LR64E-R protocol descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 docid022712 rev 7 5/141 M24LR64E-R contents 17 M24LR64E-R states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 17.1 power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 17.2 ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 17.3 quiet state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 17.4 selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 18 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 18.1 addressed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 18.2 non-addressed mode (general request) . . . . . . . . . . . . . . . . . . . . . . . . . 67 18.3 select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 19 request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 19.1 request flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 20 response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 20.1 response flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 20.2 response error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 21 anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 21.1 request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 22 request processing by the M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . 74 23 explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 24 inventory initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 25 timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25.1 t1: M24LR64E-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25.2 t2: vcd new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25.3 t 3 : vcd new request delay when no response is received from the M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 26 command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 26.1 inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 26.2 stay quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 contents M24LR64E-R 6/141 docid022712 rev 7 26.3 read single block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 26.4 write single block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 26.5 read multiple block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 26.6 select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 26.7 reset to ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 26.8 write afi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 26.9 lock afi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 26.10 write dsfid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 26.11 lock dsfid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 26.12 get system info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 26.13 get multiple block security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 26.14 write-sector password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 26.15 lock-sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 26.16 present-sector password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 26.17 fast read single block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 26.18 fast inventory initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 26.19 fast initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 26.20 fast read multiple block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 26.21 inventory initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 26.22 initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 26.23 readcfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 26.24 writeehcfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 26.25 writedocfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 26.26 setrstehen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 26.27 checkehen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 27 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 28 i 2 c dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 29 rf electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 30 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 31 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 docid022712 rev 7 7/141 M24LR64E-R contents appendix a anticollision algorithm (informative) . . . . . . . . . . . . . . . . . . . . . . . 136 a.1 algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 appendix b crc (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 b.1 crc error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 b.2 crc calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 appendix c application family identifier (afi) (informative) . . . . . . . . . . . . . . 139 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 list of tables M24LR64E-R 8/141 docid022712 rev 7 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3. address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. sector details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. sector security status byte area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. sector security status byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 table 8. read/write protection bit setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. password control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. password system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. M24LR64E-R sector security protection after power- up . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. M24LR64E-R sector security protection after a valid presentation of password 1 . . . . . . . 26 table 13. i2c_write_lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14. configuration byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 15. control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 16. eh_enable bit value after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17. system parameter sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 18. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 19. 10% modulation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 20. response data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 21. uid format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 22. crc transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 23. vcd request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 24. M24LR64E-R response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 25. M24LR64E-R response depending on request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 26. general request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 27. definition of request flags 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 28. request flags 5 to 8 when bit 3 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 29. request flags 5 to 8 when bit 3 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 30. general response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 31. definitions of response flags 1 to 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 32. response error code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 33. inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 34. example of the addition of 0-bits to an 11-bit ma sk value . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 35. timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 36. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 37. inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 38. inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 39. stay quiet request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 40. read single block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 41. read single block response format when error_fl ag is not set . . . . . . . . . . . . . . . . . . . . 83 table 42. sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 43. read single block response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 83 table 44. write single block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 45. write single block response format when error_fl ag is not set . . . . . . . . . . . . . . . . . . . . 84 table 46. write single block response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 85 table 47. read multiple block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 48. read multiple block response format when error_ flag is not set. . . . . . . . . . . . . . . . . . . 88 docid022712 rev 7 9/141 M24LR64E-R list of tables table 49. sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 50. read multiple block response format when error_fl ag is set . . . . . . . . . . . . . . . . . . . . . . . 88 table 51. select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 52. select block response format when error_flag is not set. . . . . . . . . . . . . . . . . . . . . . . . . 89 table 53. select response format when erro r_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 54. reset to ready request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 55. reset to ready response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . 91 table 56. reset to ready response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 57. write afi request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 58. write afi response format when error_flag is no t set . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 59. write afi response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 60. lock afi request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 61. lock afi response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 62. lock afi response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 63. write dsfid request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 64. write dsfid response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . 95 table 65. write dsfid response format when error_flag is se t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 66. lock dsfid request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 67. lock dsfid response format when error_flag is no t set . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 68. lock dsfid response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 69. get system info request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 70. get system info response form at when protocol_extension_flag = 0 and error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 71. get system info response form at when protocol_extension_flag = 1 and error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 72. get system info response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 73. get multiple block security status request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 74. get multiple block security status respon se format when error_flag is not set . . . . . . 100 table 75. sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 76. get multiple block security status response format when error_flag is set . . . . . . . . . . . 100 table 77. write-sector password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 78. write-sector password response format when er ror_flag is not set . . . . . . . . . . . . . . . 101 table 79. write-sector password response format when error_ flag is set . . . . . . . . . . . . . . . . . . . . 101 table 80. lock-sector request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 81. sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 82. lock-sector response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . 103 table 83. lock-sector response format when error_flag is set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 84. present-sector password request fo rmat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 85. present-sector password response format when error_flag is not set . . . . . . . . . . . . . 104 table 86. present-sector password response format when er ror_flag is set . . . . . . . . . . . . . . . . . . 104 table 87. fast read single block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 88. fast read single block response format when error_flag is not set . . . . . . . . . . . . . . . 106 table 89. sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 90. fast read single block response format when er ror_flag is set . . . . . . . . . . . . . . . . . . . 106 table 91. fast inventory initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07 table 92. fast inventory initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 93. fast initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 94. fast initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 95. fast read multiple block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 96. fast read multiple block response format when error_flag is not set. . . . . . . . . . . . . . 109 table 97. sector security status if option_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 10 table 98. fast read multiple block response format when error_flag is set . . . . . . . . . . . . . . . . . . 110 list of tables M24LR64E-R 10/141 docid022712 rev 7 table 99. inventory initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 100. inventory initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 101. initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 102. initiate response form at . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 103. readcfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 104. readcfg response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 105. readcfg response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 106. writeehcfg request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 107. writeehcfg response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . 114 table 108. writeehcfg response format when error_flag is se t . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 109. writedocfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 110. writedocfg response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . 116 table 111. writedocfg response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 112. setrstehen request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 113. setrstehen response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . 117 table 114. setrstehen response format when error_flag is se t . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 115. checkehen request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 116. checkehen response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . 118 table 117. checkehen response format when error_flag is se t . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 118. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 119. i 2 c operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 120. ac test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 121. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 122. i 2 c dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 123. i 2 c ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 124. rf characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 125. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 126. energy harvesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 127. so8n ? 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . 131 table 128. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 129. tssop8 ? 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . 133 table 130. ordering information scheme for packaged devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 131. ordering and marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 132. crc definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 133. afi coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 134. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 docid022712 rev 7 11/141 M24LR64E-R list of figures list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. i 2 c fast mode (f c = 400 khz): maximum r bus value versus bus parasitic capacitance (c bus ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. memory sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. i2c timeout on start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8. write mode sequences with i2c_write_lock bit = 1 (data write inhibited). . . . . . . . . . . . . 34 figure 9. write mode sequences with i2c_write_lock bit = 0 (data write enabled) . . . . . . . . . . . . . 35 figure 10. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 12. i 2 c present password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13. i 2 c write password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14. 100% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 15. 10% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 16. 1 out of 256 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17. detail of a time period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 18. 1 out of 4 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 19. 1 out of 4 coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 20. sof to select 1 out of 256 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 21. sof to select 1 out of 4 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 22. eof for either data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 23. logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 24. logic 0, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 25. logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 26. logic 1, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 27. logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 28. logic 0, low data rate, fast co mmands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 29. logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 30. logic 1, low data rate, fast co mmands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 31. logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 32. logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 33. logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 34. logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 35. start of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 figure 36. start of frame, high data rate, one subcarrier , fast commands. . . . . . . . . . . . . . . . . . . . . . 56 figure 37. start of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 figure 38. start of frame, low data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 57 figure 39. start of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 figure 40. start of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 figure 41. end of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 42. end of frame, high data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 58 figure 43. end of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 figure 44. end of frame, low data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 58 figure 45. end of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 46. end of frame, low da ta rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 47. M24LR64E-R decision tree for af i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 list of figures M24LR64E-R 12/141 docid022712 rev 7 figure 48. M24LR64E-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 49. M24LR64E-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 figure 50. principle of comparison between the mask, th e slot number and the uid . . . . . . . . . . . . . 73 figure 51. description of a po ssible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 52. m24lr64e rf-busy management following inv entory command . . . . . . . . . . . . . . . . . . . 81 figure 53. stay quiet frame exchange between vcd and m 24lr64e-r . . . . . . . . . . . . . . . . . . . . . . 82 figure 54. read single block frame exchange between vcd and M24LR64E-R. . . . . . . . . . . . . . . . 84 figure 55. write single block frame exchange between vcd and M24LR64E-R . . . . . . . . . . . . . . . . 85 figure 56. m24lr64e rf-busy management following write command . . . . . . . . . . . . . . . . . . . . . . 86 figure 57. m24lr64e rf-wip management following write co mmand . . . . . . . . . . . . . . . . . . . . . . . 87 figure 58. read multiple block frame exchange betwee n vcd and M24LR64E-R . . . . . . . . . . . . . . 89 figure 59. select frame exchange between vcd and m24lr64e -r . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 60. reset to ready frame exchange between vcd and M24LR64E-R . . . . . . . . . . . . . . . . . . 91 figure 61. write afi frame exchange between vcd and m24lr 64e-r . . . . . . . . . . . . . . . . . . . . . . . 92 figure 62. lock afi frame exchange between vcd and m24lr6 4e-r . . . . . . . . . . . . . . . . . . . . . . . 94 figure 63. write dsfid frame exchange between vcd and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 96 figure 64. lock dsfid frame exchange between vcd and M24LR64E-R. . . . . . . . . . . . . . . . . . . . . 97 figure 65. get system info frame exchange between vc d and M24LR64E-R . . . . . . . . . . . . . . . . . 99 figure 66. get multiple block security status frame exchange between vcd and M24LR64E-R . . 100 figure 67. write-sector password frame exchange between vcd and M24LR64E-R . . . . . . . . . . . 102 figure 68. lock-sector frame exchange between vcd and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 103 figure 69. present-sector password frame exchange between vcd and M24LR64E-R . . . . . . . . . 105 figure 70. fast read single block frame exchange between vcd and M24LR64E-R. . . . . . . . . . . 106 figure 71. fast initiate frame exchange between vcd a nd M24LR64E-R . . . . . . . . . . . . . . . . . . . . 108 figure 72. fast read multiple block frame exchange between vcd and M24LR64E-R . . . . . . . . . 110 figure 73. initiate frame exchange between vcd and m24l r64e-r . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 74. readcfg frame exchange between vcd and m24l r64e-r . . . . . . . . . . . . . . . . . . . . . . 113 figure 75. writeehcfg frame exchange between vcd and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 115 figure 76. writedocfg frame exchange between vcd and M24LR64E-R. . . . . . . . . . . . . . . . . . . . 116 figure 77. setrstehen frame exchange between vcd a nd M24LR64E-R . . . . . . . . . . . . . . . . . . . 117 figure 78. checkehen frame exchange between vcd and M24LR64E-R. . . . . . . . . . . . . . . . . . . . 119 figure 79. ac test measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 80. i 2 c ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 81. ask modulated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 82. energy harvesting: vout min vs. isink. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 83. energy harvesting: working domain range 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 84. energy harvesting: working domain range 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 85. energy harvesting: working domain range 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 86. energy harvesting: working domain range 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 87. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 131 figure 88. ufdfpn8 (mlp8) ? 8-lead ultra th in fine pitch dual flat package no lead 2 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 89. tssop8 ? 8-lead thin shrink small outline, pa ckage outline . . . . . . . . . . . . . . . . . . . . . . 133 docid022712 rev 7 13/141 M24LR64E-R description 1 description the M24LR64E-R device is a dyna mic nfc/rfid tag ic with a du al-interface, electrically erasable programmable memory (eeprom). it features an i 2 c interface and can be operated from a v cc power supply. it is also a contactless memory powered by the received carrier electromagnetic wave. the M24LR64E-R is organized as 8192 8 bits in the i 2 c mode and as 2048 32 bits in the iso 15693 and iso 18000-3 mode 1 rf mode. the M24LR64E-R also features an energy harvesting analog output, as well as a user- configurable digital output pin toggling during either rf write in progress or rf busy mode. figure 1. logic diagram i 2 c uses a two-wire serial interface, comprising a bidirectional data line and a clock line. the devices carry a built-in 4-bit device type identi fier code (1010) in accordance with the i 2 c bus definition. the device behaves as a slave in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and read/write bit (rw ) (as described in table 2 ), terminated by an acknowledge bit. when writing data to the memory, the device inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. in the iso15693/iso18000-3 mode 1 rf mo de, the M24LR64E-R is accessed via the 13.56 mhz carrier electromagnetic wave on which incoming data is demodulated from the received signal amplitude modu lation (ask: amplitud e shift keying). when connected to an antenna, the operating power is derived from the rf energy and no external power supply is required. the received ask wave is 10% or 100% modulated with a data rate of 1.6 kbit/s 9 & & 0 / 5 ( 5 6 & / 6 ' $ $ & $ & 0 6 y 9 9 r x w 5 ) : , 3 % 8 6 < 9 6 6 description M24LR64E-R 14/141 docid022712 rev 7 using the 1/256 pulse coding mode or a data ra te of 26 kbit/s using the 1/4 pulse coding mode. outgoing data is generated by the m24lr64e -r load variation using manchester coding with one or two subcarrier frequencies at 423 khz and 484 khz. data is transferred from the M24LR64E-R at 6.6 kbit/s in low data rate mode and 26 kbit/s in high data rate mode. the M24LR64E-R supports the 53 kbit/s fast mode in high data rate mode using one subcarrier frequency at 423 khz. the M24LR64E-R follows the iso 15693 and iso 18000-3 mode 1 recommendation for radio-frequency power and signal interface. the M24LR64E-R provides an energy harves ting mode on the analog output pin vout. when the energy harvesting mode is activa ted, the M24LR64E-R can output the excess energy coming from the rf field on the vout an alog pin. in case the rf field strength is insufficient or when energy harvesting mode is disabled, the analog output pin vout goes into high-z state and energy harvesting mode is automatically stopped. the M24LR64E-R features a user configurable digital out pin rf wip/busy that can be used to drive a microcontroller interrupt input pin (available only when the M24LR64E-R is correctly powered on the vcc pin). when configured in the rf write in progress mode (rf wip mode), the rf wip/busy pin is driven low for the entire duration of the rf internal write operation. when configured in the rf busy mode (rf busy mode), the rf wip/busy pin is driven low for the entire duration of the rf command progress. the rf wip/busy pin is an open drain output a nd must be connected to a pull-up resistor. figure 2. 8-pin package connections 1. see section 30 for package dimensions, and how to identify pin 1. table 1. signal names signal name function direction vout energy harvesting output analog output sda serial data i/o scl serial clock input ac0, ac1 antenna coils i/o v cc supply voltage - rf wip/busy digital signal digital output v ss ground - 3 $ ! 6 3 3 3 # , 2 & 7 ) 0 " 5 3 9 ! # 6 o u t 6 # # - 3 6 ! # docid022712 rev 7 15/141 M24LR64E-R signal descriptions 2 signal descriptions 2.1 serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from serial clock (scl) to v cc . ( figure 3 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of syn chronization is not employed, and so the pull- up resistor is not necessary, provided that th e bus master has a push-pull (rather than open drain) output. 2.2 serial data (sda) this bidirectional signal is used to transfer dat a in or out of the device. it is an open drain output that may be wire-or?ed with other open dr ain or open collector signals on the bus. a pull-up resistor must be connected from serial data (sda) to v cc . ( figure 3 indicates how the value of the pull-up resistor can be calculated). 2.3 rf write in progress / rf busy (rf wip/busy) this configurable output signal is used either to indicate that the M24LR64E-R is executing an internal write cycle from the rf channel or that an rf command is in progress. rf wip and signals are available only when the m24lr64e -r is powered by the vcc pin. it is an open drain output and a pull-up resistor mu st be connected from rf wip/busy to v cc . 2.4 energy harvesting analog output (vout) this analog output pin is used to deliver the analog voltage vout available when the energy harvesting mode is enabled and the rf field strength is sufficient. when the energy harvesting mode is disabled or the rf field st rength is not sufficien t, the energy harvesting analog voltage output vout is in high-z state. 2.5 antenna coil (ac0, ac1) these inputs are used to connect the device to an external coil exclusively. it is advised not to connect any other dc or ac path to ac0 or ac1. when correctly tuned, the coil is used to power and access the device using the iso 15693 and iso 18000-3 mode 1 protocols. 2.5.1 device reset in rf mode to ensure a proper reset of the rf circuitry, the rf field must be turned off (100% modulation) for a minimum t rf_off period of time. signal descriptions M24LR64E-R 16/141 docid022712 rev 7 2.6 v ss ground v ss is the reference for the v cc supply voltage and vout analog output voltage. 2.7 supply voltage (v cc ) this pin can be connected to an external dc supply voltage. note: an internal voltage regulator allows the external voltage applied on v cc to supply the M24LR64E-R, while preventing the internal powe r supply (rectified rf waveforms) to output a dc voltage on the v cc pin. 2.7.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see table 119 ). to maintain a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually around 10 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instruction, until the co mpletion of the internal i2c write cycle (t w ). 2.7.2 power-up conditions when the power supply is turned on, v cc rises from v ss to v cc . the v cc rise time must not vary faster than 1v/s. 2.7.3 device reset in i2c mode in order to prevent inadvertent write operations during power-up, a power-on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device does not respond to any i2c instruction until v cc has reached the power-on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in table 119 ). when v cc passes over the por threshold, the device is reset and enters the standby power mode. however, the device must not be accessed until v cc has reached a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range. in a similar way, during power-down (continuous decrease in v cc ), as soon as v cc drops below the power-on reset threshold voltage, t he device stops responding to any instruction sent to it. 2.7.4 power-down conditions during power-down (continuous decay of v cc ), the device must be in standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress). docid022712 rev 7 17/141 M24LR64E-R signal descriptions figure 3. i 2 c fast mode (f c = 400 khz): maximum r bus value versus bus parasitic capacitance (c bus ) figure 4. i 2 c bus protocol a i b " u s l i n e c a p a c i t o r p & " u s l i n e p u l l u p r e s i s t o r k ) # b u s m a s t e r - x x x 2 b u s 6 # # # b u s 3 # , 3 $ ! 2 b u s # b u s n s ( e r e 2 b u s # b u s n s k ? p & 4 h e 2 x # t i m e c o n s t a n t m u s t b e b e l o w t h e n s t i m e c o n s t a n t l i n e r e p r e s e n t e d o n t h e l e f t b u s b u s 3 # , 3 $ ! 3 # , 3 $ ! 3 $ ! 3 4 ! 2 4 # o n d i t i o n 3 $ ! ) n p u t 3 $ ! # h a n g e ! ) " 3 4 / 0 # o n d i t i o n - 3 " ! # + 3 4 ! 2 4 # o n d i t i o n 3 # , - 3 " ! # + 3 4 / 0 # o n d i t i o n signal descriptions M24LR64E-R 18/141 docid022712 rev 7 table 2. device select code device type identifier (1) 1. the most significant bi t, b7, is sent first. chip enable address rw b7 b6 b5 b4 b3 b2 b1 b0 device select code1010e2 (2) 2. e2 is not connected to any external pin. it is however used to address the M24LR64E-R as described in section 3 and section 4 . 11rw table 3. address most significant byte b15 b14 b13 b12 b11 b10 b9 b8 table 4. address least significant byte b7 b6 b5 b4 b3 b2 b1 b0 docid022712 rev 7 19/141 M24LR64E-R user memory organization 3 user memory organization the M24LR64E-R is divided into 64 sectors of 32 blocks of 32 bits, as shown in table 5 . figure 6 shows the memory sector organization. each sector can be individually read- and/or write-protected using a specific pass word command. read and write operations are possible if the addressed data is not in a protected sector. the M24LR64E-R also has a 64-bit block that is used to store the 64-bit unique identifier (uid). the uid is compliant with the iso 15963 description, and its value is used during the anticollision sequence (inventory). this block is not accessible by the user in rf device operation and its value is writte n by st on the production line. the M24LR64E-R includes an afi register that stores the application family identifier, and a dsfid register that stores the data storage family id entifier used in the anticollision algorithm. the M24LR64E-R has four 32-b it blocks that store an i 2 c password plus three rf password codes. figure 5. circuit diagram 0 6 9 5 ) 9 & & $ & $ & 5 ) 3 r z h u p d q d j h p h q w 9 r x w 5 ) : , 3 % 8 6 < / r j l f ( ( 3 5 2 0 / d w f k , & & r q w d f w 9 & & 6 & / 6 ' $ 9 & & 9 6 6 5 r z g h f r g h u user memory organization M24LR64E-R 20/141 docid022712 rev 7 figure 6. memory sector organization sector details the M24LR64E-R user memory is divided into 64 sectors. each sector contains 1024 bits. the protection scheme is described in section 4: system memory area . in rf mode, a sector provides 32 blocks of 32 bits. each read and write access is done by block. read and write block accesses are contro lled by a sector security status byte that defines the access rights to the 32 blocks c ontained in the sector. if the sector is not protected, a write command updates the complete 32 bits of the selected block. in i 2 c mode, a sector provides 128 bytes that can be individually accessed in read and write modes. when protected by the corresponding i2c_write_lo ck bit, the entire sector is write-protected. to access the user memory, the device select code used for any i 2 c command must have the e2 chip enable address at 0. 0 6 9 . e l w ( ( 3 5 2 0 v h f w r u . e l w ( ( 3 5 2 0 v h f w r u . e l w ( ( 3 5 2 0 v h f w r u . e l w ( ( 3 5 2 0 v h f w r u 6 h f w r u $ u h d 6 h f w r u v h f x u l w \ v w d w x v . e l w ( ( 3 5 2 0 v h f w r u . e l w ( ( 3 5 2 0 v h f w r u . e l w ( ( 3 5 2 0 v h f w r u . e l w ( ( 3 5 2 0 v h f w r u , e & s d v v z r u g 5 ) s d v v z r u g 5 ) s d v v z r u g 5 ) s d v v z r u g e l w ' 6 ) , ' e l w $ ) , e l w f r q i l j x u d w l r q e l w , e & : u l w h / r f n b e l w e l w 8 , ' e l w v e l w v e l w v e l w v e l w v e l w v e l w v e l w v 6 \ v w h p 6 \ v w h p 6 \ v w h p 6 \ v w h p 6 \ v w h p 6 \ v w h p 6 \ v w h p 6 \ v w h p e l w 6 6 6 6 \ v w h p docid022712 rev 7 21/141 M24LR64E-R user memory organization table 5. sector details sector number rf block address i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] 0 0 0 user user user user 1 4 user user user user 2 8 user user user user 3 12 user user user user 4 16 user user user user 5 20 user user user user 6 24 user user user user 7 28 user user user user 8 32 user user user user 9 36 user user user user 10 40 user user user user 11 44 user user user user 12 48 user user user user 13 52 user user user user 14 56 user user user user 15 60 user user user user 16 64 user user user user 17 68 user user user user 18 72 user user user user 19 76 user user user user 20 80 user user user user 21 84 user user user user 22 88 user user user user 23 92 user user user user 24 96 user user user user 25 100 user user user user 26 104 user user user user 27 108 user user user user 28 112 user user user user 29 116 user user user user 30 120 user user user user 31 124 user user user user user memory organization M24LR64E-R 22/141 docid022712 rev 7 1 32 128 user user user user 33 132 user user user user 34 136 user user user user 35 140 user user user user 36 144 user user user user 37 148 user user user user 38 152 user user user user 39 156 user user user user ... ... ... ... ... ... ... ... ... ... ... ... ... table 5. sector details (continued) sector number rf block address i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] docid022712 rev 7 23/141 M24LR64E-R user memory organization 63 2016 8064 user user user user 2017 8068 user user user user 2018 8072 user user user user 2019 8076 user user user user 2020 8080 user user user user 2021 8084 user user user user 2022 8088 user user user user 2023 8092 user user user user 2024 8096 user user user user 2025 8100 user user user user 2026 8104 user user user user 2027 8108 user user user user 2028 8112 user user user user 2029 8116 user user user user 2030 8120 user user user user 2031 8124 user user user user 2032 8128 user user user user 2033 8132 user user user user 2034 8136 user user user user 2035 8140 user user user user 2036 8144 user user user user 2037 8148 user user user user 2038 8152 user user user user 2039 8156 user user user user 2040 8160 user user user user 2041 8164 user user user user 2042 8168 user user user user 2043 8172 user user user user 2044 8176 user user user user 2045 8180 user user user user 2046 8184 user user user user 2047 8188 user user user user table 5. sector details (continued) sector number rf block address i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] system memory area M24LR64E-R 24/141 docid022712 rev 7 4 system memory area 4.1 M24LR64E-R block security in rf mode the M24LR64E-R provides a spec ial protection mechanism based on passwords. in rf mode, each memory sector of the M24LR64E-R can be individually protected by one out of three available passwords, and each sector can also have read/write access conditions set. each memory sector of the M24LR64E-R is as signed with a sector security status byte including a sector lock bit, two password control bits and two read/write protection bits, as shown in table 7 . table 6 describes the organization of the sector security status byte, which can be read using the read single block and read multiple block commands with the option_flag set to 1. on delivery, the default value of the sss bytes is set to 00h. table 6. sector security status byte area i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] e2 = 1 0 sss 3 sss 2 sss 1 sss 0 e2 = 1 4 sss 7 sss 6 sss 5 sss 4 e2 = 1 8 sss 11 sss 10 sss 9 sss 8 e2 = 1 12 sss 15 sss 14 sss 13 sss 12 e2 = 1 16 sss 19 sss 18 sss 17 sss 16 e2 = 1 20 sss 23 sss 22 sss 21 sss 20 e2 = 1 24 sss 27 sss 26 sss 25 sss 24 e2 = 1 28 sss 31 sss 30 sss 29 sss 28 e2 = 1 32 sss 35 sss 34 sss 33 sss 32 e2 = 1 36 sss 39 sss 38 sss 37 sss 36 e2 = 1 40 sss 43 sss 42 sss 41 sss 40 e2 = 1 44 sss 47 sss 46 sss 45 sss 44 e2 = 1 48 sss 51 sss 50 sss 49 sss 48 e2 = 1 52 sss 55 sss 54 sss 53 sss 52 e2 = 1 56 sss 59 sss 58 sss 57 sss 56 e2 = 1 60 sss 63 sss 62 sss 61 sss 60 table 7. sector security status byte organization b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 0 password control bits read / write protection bits sector lock docid022712 rev 7 25/141 M24LR64E-R system memory area when the sector lock bit is set to 1, for instance by issuing a lock-sector command, the two read/write protection bits (b 1 , b 2 ) are used to set the read/write access of the sector as described in table 8 . the next two bits of the sect or security status byte (b 3 , b 4 ) are the password control bits. the value of these two bits is used to link a password to the sector, as defined in table 9 . the M24LR64E-R password protection is orga nized around a dedicated set of commands, plus a system area of three password blocks wh ere the password values are stored. this system area is described in table 10 . the dedicated commands for protection in rf mode are: ? write-sector password: the write-sector password command is used to write a 32-bit block into the password system area. this command must be used to update password values. after the write cycle, the new password value is automatically activated. it is possible to modify a password value after issuing a valid presen t-sector password command. on delivery, the three default password values are set to 0000 0000h and are activated. ? lock-sector: the lock-sector command is used to set the se ctor security status byte of the selected sector. bits b 4 to b 1 of the sector security status byte are affected by the lock-sector table 8. read/write protection bit setting sector lock b 2 , b 1 sector access when password presented sector access when password not presented 0 xx read write read write 1 00 read write read no write 1 01 read write read write 1 10 read write no read no write 1 11 read no write no read no write table 9. password control bits b 4 , b 3 password 00 the sector is not pr otected by a password. 01 the sector is protected by password 1. 10 the sector is protected by password 2. 11 the sector is protected by password 3. table 10. password system area add password 1 password 1 2 password 2 3 password 3 system memory area M24LR64E-R 26/141 docid022712 rev 7 command. the sector lock bit, b 0 , is set to 1 automatically. after issuing a lock-sector command, the protection settings of the selected sector are activated. the protection of a locked block cannot be changed in rf mode. a lock-sector command sent to a locked sector returns an error code. ? present-sector password: the present-sector password command is used to present one of the three passwords to the M24LR64E-R in order to modify the access rights of all the memory sectors linked to that password ( table 8 ) including the password itself. if the presented password is correct, the access rights rema in activated until the tag is powered off or until a new present-sector password comm and is issued. if the presented password value is not correct, all the access rights of all the memory sectors are deactivated. ? sector security status byte area access co nditions in i 2 c mode: in i 2 c mode, read access to the sector security status byte area is always allowed. write access depends on the correct presentation of the i 2 c password (see section 5.16.1: i2c present password command description ). to access the sector security status byte ar ea, the device select code used for any i 2 c command must have the e2 chip enable address at 1. an i 2 c write access to a sector security status byte re-i nitializes the rf access condition to the given memory sector. 4.1.1 example of the M24LR64E-R security protection in rf mode table 11 and table 12 show the sector security protecti ons before and after a valid present- sector password command. table 11 shows the sector access rights of an M24LR64E-R after power-up. after a valid present-sect or password command with password 1, the memory sector access is changed as shown in table 12 . table 11. M24LR64E-R sector security protection after power-up sector address sector features sector security status byte b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 protection: standard read no write xxx 00001 1 protection: pswd 1 read no write xxx 01001 2 protection: pswd 1 read write xxx 01011 3 protection: pswd 1 no read no write xxx 01101 4 protection: pswd 1 no read no write xxx 01111 table 12. M24LR64E-R sector security protection after a valid presentation of password 1 sector address sector features sector security status byte b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 protection: standard read no write xxx 00001 1 protection: pswd 1 read write xxx 01001 2 protection: pswd 1 read write xxx 01011 docid022712 rev 7 27/141 M24LR64E-R system memory area 4.2 M24LR64E-R block security in i2c mode (i2c_write_lock bit area) in the i 2 c mode only, it is possible to protect individual sectors against write operations. this feature is controlled by the i2c_write_lock bits stored in the 8 bytes of the i2c_write_lock bit area. i2c_write_lock bit area starts from location 8192 (see table 13 ). to access the i2c_write_lock bit area, th e device select code used for any i 2 c command must have the e2 chip enable address at 1. using these 16 bits, it is possible to write-protect all the 64 sectors of the M24LR64E-R memory. each bit controls the i 2 c write access to a specif ic sector as shown in table 13 . it is always possible to unpro tect a sector in the i 2 c mode. when an i2c_write_lock bit is reset to 0, the corresponding sector is un protected. when the bi t is set to 1, the corresponding sector is write-protected. in i 2 c mode, read access to the i2 c_write_lock bit area is always allowed. write access depends on the correct presentation of the i 2 c password. on delivery, the default value of the eight bytes of the i2c_write_lock bit area is reset to 00h. 4.3 configuration byte and control register the M24LR64E-R offers an 8-bit non-volatile configuration byte located at i2c location 2320 of the system area used to store the rf wip/busy pin and the energy harvesting configuration (see table 14 ). the M24LR64E-R also offers an 8-bit volatile c ontrol register located at i2c location 2336 of the system area used to store the energy harvesting enable bit as well as a field_on bit indicator (see table 15 ). 4.3.1 rf wip/busy pin configuration the M24LR64E-R features a configurable op en drain output rf wip/busy pin used to provide rf activity informat ion to an external device. 3 protection: pswd 1 read write xxx 01101 4 protection: pswd 1 read no write xxx 01111 table 12. M24LR64E-R sector security protection after a valid presentation of password 1 (continued) sector address sector features sector security status byte b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 table 13. i2c_write_lock bit i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] e2 = 1 2048 sectors 31-24 sectors 23-16 sectors 15-8 sectors 7-0 e2 = 1 2052 sectors 63-56 sectors 55-48 sectors 47-40 sectors 39-32 system memory area M24LR64E-R 28/141 docid022712 rev 7 the rf wip/busy pin functionality depends on th e value of bit 3 of th e configuration byte. ? rf busy mode when bit 3 of the configuration byte is set to 0, the rf wip/busy pin is configured in rf busy mode. the purpose of this mode is to indicate to the i2c bus master whether the M24LR64E-R is busy in rf mode or not. in this mode, the rf wip/busy pin is tied to 0 from the rf command start of frame (sof) until the end of the command execution. if a bad rf command is received, the rf wip/ busy pin is tied to 0 from the rf command sof until the reception of the rf command crc. otherwise, the rf wip/busy pin is in high-z state. when tied to 0, the rf wip/busy signal return s to high-z state if the rf field is cut-off. during the execution of i2c commands, the rf wip/busy pin remains in high-z state. ? rf write in progress when bit 3 of the configuration byte is set to 1, the rf wip/busy pin is configured in rf write in progress mode. the purpose of this mode is to indicate to the i2c bus master that some data has been changed in rf mode. in this mode, the rf wip/busy pin is tied to 0 for the duration of an internal write operation (i.e. between the end of a valid rf write command and the beginning of the rf answer). during the execution of i2c write operations, the rf wip/busy pin remains in high-z state. 4.3.2 energy harvest ing configuration the M24LR64E-R features an energy harv esting mode on the vout analog output. the general purpose of the energy harvesti ng mode is to deliver a part of the non- necessary rf power received by the M24LR64E-R on the ac0-ac1 rf input in order to supply an external device. the current consum ption on the analog voltage output vout is limited to ensure that the M24LR64E-R is correctly supplied during the powering of the external device. when the energy harvesting mode is enabled and the power delivered on the ac0-ac1 rf input exceeds the minimum required p ac0-ac1_min , the M24LR64E-R is able to deliver a limited and unregulated voltage on the vout pi n, assuming the current consumption on the vout does not exceed the i sink_max maximum value. if one of the conditions above is not met, the a nalog voltage output pin vout is set in high-z state. for robust applications using the energy harvest ing mode, four current fan-out levels can be chosen. docid022712 rev 7 29/141 M24LR64E-R system memory area ? vout sink current configuration the sink current level is chosen by pr ogramming eh_cfg1 an d eh_cfg0 into the configuration byte (see table 14 ). the minimum power level required on ac0-ac1 rf input p ac0-ac1_min , the delivered voltage vout, as well as the maximum current consumption i sink_max on the vout pin corresponding to the system memory area M24LR64E-R 30/141 docid022712 rev 7 4.3.3 field_on indicator bit the field_on indicator bit located as bit 1 of the control register is a read-only bit used to indicate when the rf power level delivered to the M24LR64E-R is sufficient to execute rf commands. ? when field_on = 0, the M24LR64E-R is not able to execute any rf commands. ? when field_on =1, the M24LR64E-R is able to execute any rf commands. note: during read access to the control register in rf mode, the field_ on bit is always read at 1. 4.3.4 configuration byte access in i2c and rf modes in i2c mode, read and write accesses to the non-volatile configuration byte are always allowed. to access the configuration byte, the device select code used for any i2c command must have the e2 chip enable address at 1. the dedicated commands to access the configuration byte in rf mode are: ? read configuration byte command (readcfg): ? the readcfg command is used to read the eight bits of the configuration byte. ? write energy harvesting conf iguration command (writeehcfg): ? the writeehcfg command is used to writ e the eh_mode, eh_cfg1 and eh_cfg0 bits into the configuration byte. ? write rf wip/busy pin configuration command (writedocfg): ? the writedocfg command is used to write the rf wip/busy bit into the configuration byte. after any write access to the configuration byte, the new configurat ion is automatically applied. 4.3.5 control register access in i2c or rf mode in i2c mode, read and write accesses to the volatile control register are always allowed. to access the control register, the device select code used for any i2c command must have the e2 chip enable address at 1. the dedicated commands to access the control register in rf mode are: ? check energy harvesting enable bit command (checkehen): ? the checkehen command is used to read th e eight bits of the control register. when it is run, the field_on bit is always read at 1. ? set/reset energy harvesting enable bit command (setrstehen): ? the setrstehen command is used to set or reset the value of the eh_enable bit into the control register. 4.4 iso 15693 syst em parameters the M24LR64E-R provides the system area re quired by the iso 15693 rf protocol, as shown in table 17 . the first 32-bit block starting from i 2 c address 2304 stores the i 2 c password. this password is used to activate/deactivate the write protection of the protected sector in i 2 c docid022712 rev 7 31/141 M24LR64E-R system memory area mode. at power-on, all user memory sectors protected by the i2c_write_lock bits can be read but cannot be modified. to remove the wr ite protection, it is necessary to use the i 2 c present password described in figure 12 . when the password is correctly presented ? that is, when all the presented bits correspond to the stored ones ? it is also possible to modify the i 2 c password using the i 2 c write password command described in figure 13 . the next three 32-bit blocks store the three rf passwords. these passwords are neither read- nor write- accessible in the i 2 c mode. the next byte stores the configuration byte, at i2c location 2320. this control register is used to store the three energy harvestin g configuration bits and the rf wip/busy configuration bit. the next two bytes are used to store the afi, at i 2 c location 2322, and the dsfid, at i 2 c location 2323. these two values are used during the rf inventory sequence. they are read-only in the i 2 c mode. the next eight bytes, starting from location 2324, store the 64-bit uid programmed by st on the production line. bytes at i 2 c locations 2332 to 2335 store the ic ref and the mem_size data used by the rf get_system_info command. the uid, mem_size and ic ref values are read-only data. table 17. system parameter sector i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] e2 = 1 2304 i 2 c password (1) 1. delivery state: i 2 c password = 0000 0000h, rf password = 0000 0000h, configuration byte = f4h e2 = 1 2308 rf password 1 (1) e2 = 1 2312 rf password 2 (1) e2 = 1 2316 rf password 3 (1) e2 = 1 2320 dsfid (ffh) afi (00h) st reserved (exh) (2) 2. the product revision is the most significant nibble of the byte located at address 0x911 (2321 d) in the system area (device select code e2 =1). from ds rev4, the product revision value is 0xe. the least significant nibble is st reserved. configuration byte (f4h) e2 = 1 2324 uid uid uid uid e2 = 1 2328 uid (e0h) uid (02h) uid uid e2 = 1 2332 mem_size (03 07ffh) ic ref (5eh) e2 = 1 2336 - - - prog. completion and energy harvesting status (3) 3. address system 2336 (920h, e2 =1) is the control register. bit 7 is t_prog (refer to table 15: control register ). when accessed in rf, this bit is not significant and set to 0. bits 2-6 are rfu and set to 0. bit 1 is field_on (refer to table 15: control register ). bit 0 is eh_enable (refer to table 15: control register ). i 2 c device operation M24LR64E-R 32/141 docid022712 rev 7 5 i 2 c device operation the device supports the i 2 c protocol. this is summarized in figure 4 . any device that sends data to the bus is defined as a transmitter, and any device that reads data is defined as a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can only be initiated by the bus master, which also provides the serial clock for synchronization. the M24LR64E-R device is a slave in all communications. 5.1 start condition start is identified by a falling edge of serial data (sda) while the serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a wr ite cycle) the sda and the scl for a start condition, and does not respond unless one is given. 5.2 stop condition stop is identified by a rising edge of serial data (sda) while the serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the standby mode. a st op condition at the end of a write command triggers the inte rnal write cycle. 5.3 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether a bus master or a slave device, releas es the serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls the sda low to acknowledge the receipt of the eight data bits. 5.4 data input during data input, the device samples serial da ta (sda) on the rising edge of the serial clock (scl). for correct device operation, the sda must be stable during the rising edge of the scl, and the sda signal must change only when the scl is driven low. 5.5 i2c timeout during the execution of an i2c operatio n, rf communications are not possible. to prevent rf communication freezing due to in advertent unterminated in structions sent to the i2c bus, the M24LR64E-R features a timeou t mechanism that automatically resets the i2c logic block. docid022712 rev 7 33/141 M24LR64E-R i 2 c device operation 5.5.1 i2c timeout on start condition i2c communication with the M24LR64E-R starts with a valid start cond ition, followed by a device select code. if the delay between the start condition and the following rising edge of the serial clock (scl) that samples the most significan t of the device select exceeds the t start_out time (see table 123 ), the i2c logic block is reset and further incoming data transfer is ignored until the next valid start condition. figure 7. i2c timeout on start condition 5.5.2 i2c timeout on clock period during data transfer on the i2c bus, if the serial clock pulse width high ( t chcl ) or serial clock pulse width low ( t clch ) exceeds the maximum value specified in table 123 , the i2c logic block is reset and any further incoming data tr ansfer is ignored until the next valid start condition. 5.6 memory addressing to start a communication between the bus ma ster and the slave device, the bus master must initiate a start condition. following this, the bus master sends the device select code, shown in table 2 (on serial data (sda), the most significant bit first). the device select code consists of a 4-bit device type identifier and a 3-bit chip enable ?address? (e2,1,1). to address the memory array, the 4-bit device type identifier is 1010b. refer to table 2 . the eighth bit is the read/write bit (rw ). it is set to 1 for read and to 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the ninth bit time. if the device does not match the device select code, it de selects itself from the bus, and goes into standby mode. 0 6 9 6 & / 6 ' $ w 6 7 $ 5 7 b 2 8 7 6 w d u w f r q g l w l r q i 2 c device operation M24LR64E-R 34/141 docid022712 rev 7 figure 8. write mode sequences with i2c_write_lock bit = 1 (data write inhibited) 5.7 write operations following a start condition, the bus master sends a device select code with the read/write bit (rw ) reset to 0. the device acknowledges this, as shown in figure 8 , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if t he i2c_write_lock bit = 1. a write instruction issued with the i2c_write_lock bit = 1 and with no i2c_password presented does not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in figure 8 . each data byte in the memory has a 16-bit (t wo-byte wide) address. the most significant byte ( table 3 ) is sent first, followed by the least significant byte ( table 4 ). bits b15 to b0 form the address of the byte in memory. table 18. operating modes mode rw bit bytes initial sequence current address read 1 1 start, device select, rw = 1 random address read 0 1 start, device select, rw = 0, address 1 restart, device select, rw = 1 sequential read 1 1 similar to current or random address read byte write 0 1 start, device select, rw = 0 page write 0 4 bytes start, device select, rw = 0 3 t o p 3 t a r t " y t e 7 r i t e $ e v s e l e c t " y t e a d d r e s s " y t e a d d r e s s $ a t a i n 3 t a r t 0 a g e 7 r i t e $ e v s e l e c t " y t e a d d r e s s " y t e a d d r e s s $ a t a i n $ a t a i n ! ) 0 a g e 7 r i t e c o n t g d 3 t o p $ a t a i n . ! # + ! # + ! # + . / ! # + 2 7 ! # + ! # + ! # + . / ! # + 2 7 . / ! # + . / ! # + docid022712 rev 7 35/141 M24LR64E-R i 2 c device operation when the bus master generates a stop conditio n immediately after the ack bit (in the tenth- bit time slot), either at the end of a byte writ e or a page write, the internal write cycle is triggered. a stop condition at any other time slot does not trigger th e internal write cycle. after the stop condition, the delay t w , and the successful completion of a write operation, the device?s internal address counter is increm ented automatically, to point to the next byte address after the last one that was modified. during the internal write cycle, the serial data (sda) signal is disabled internally, and the device does not respond to any requests. 5.8 byte write after the device select code and the address byte s, the bus master send s one data byte. if the addressed location is write- protected by the i2c_write_lock bit (= 1), the device replies with noack, and the location is not modified. if the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 9 . 5.9 page write the page write mode allows up to four bytes to be written in a single write cycle, provided that they are all located in the same ?row? in the memory: that is, the most significant memory address bits (b12-b2) are the same. if mo re bytes are sent than fit up to the end of the row, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation-dependent way. the bus master sends from one to four bytes of data, each of which is acknowledged by the device if the i2c_write_lock bit = 0 or the i2c_password was correctly presented. if the i2c_write_lock_bit = 1 and the i2c_password are not presented, the contents of the addressed memory location are not modified, an d each data byte is followed by a noack. after each byte is transferre d, the internal byte address counter (inside the page) is incremented. the transfer is terminated by the bus master generating a stop condition. figure 9. write mode sequences with i2c_write_lock bit = 0 (data write enabled) 3 t o p 3 t a r t " y t e 7 r i t e $ e v 3 e l e c t " y t e a d d r e s s " y t e a d d r e s s $ a t a i n 3 t a r t 0 a g e 7 r i t e $ e v 3 e l e c t " y t e a d d r e s s " y t e a d d r e s s $ a t a i n $ a t a i n ! ) 3 t o p $ a t a i n . ! # + 2 7 ! # + ! # + ! # + ! # + ! # + ! # + ! # + 2 7 ! # + ! # + i 2 c device operation M24LR64E-R 36/141 docid022712 rev 7 figure 10. write cycle polling flowchart using ack 5.10 minimizing system de lays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum i2c write time (t w ) is shown in table 123 , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 10 , is: 1. initial condition: a wr ite cycle is in progress. 2. step 1: the bus master issues a start co ndition followed by a device select code (the first byte of the new instruction). 3. step 2: if the device is busy with the internal write cycle, no ack is returned and the bus master goes back to step 1. if the device ha s terminated the intern al write cycle, it responds with an ack, indicating that the devi ce is ready to receive the second part of the instruction (the first byte of this in struction having been sent during step 1). $ , g : u l w h f \ f o h l q s u r j u h v v 1 h [ w 2 s h u d w l r q l v d g g u h v v l q j w k h p h p r u \ 6 w d u w f r q g l w l r q ' h y l f h v h o h f w z l w k 5 : $ & . u h w x u q h g < ( 6 1 2 < ( 6 1 2 5 h 6 w d u w 6 w r s ' d w d i r u w k h : u l w h r s h u d w l r q 6 h q g $ g g u h v v d q g 5 h f h l y h $ & . < ( 6 1 2 6 w d u w & r q g l w l r q & r q w l q x h w k h : u l w h r s h u d w l r q & r q w l q x h w k h 5 d q g r p 5 h d g r s h u d w l r q ' h y l f h v h o h f w z l w k 5 : ) l u v w e \ w h r i l q v w u x f w l r q z l w k 5 : d o u h d g \ g h f r g h g e \ w k h g h y l f h docid022712 rev 7 37/141 M24LR64E-R i 2 c device operation figure 11. read mode sequences 1. the seven most significant bits of the device select code of a random read (in the first and fourth bytes) must be identical. 3 t a r t $ e v s e l " y t e a d d r " y t e a d d r 3 t a r t $ e v s e l $ a t a o u t ! ) d $ a t a o u t . 3 t o p 3 t a r t # u r r e n t ! d d r e s s 2 e a d $ e v s e l $ a t a o u t 2 a n d o m ! d d r e s s 2 e a d 3 t o p 3 t a r t $ e v s e l $ a t a o u t 3 e q u e n t i a l # u r r e n t 2 e a d 3 t o p $ a t a o u t . 3 t a r t $ e v s e l " y t e a d d r " y t e a d d r 3 e q u e n t i o n 2 a n d o m 2 e a d 3 t a r t $ e v s e l $ a t a o u t 3 t o p ! # + 2 7 . / ! # + ! # + 2 7 ! # + ! # + ! # + 2 7 ! # + ! # + ! # + . / ! # + 2 7 . / ! # + ! # + ! # + ! # + 2 7 ! # + ! # + 2 7 ! # + . / ! # + i 2 c device operation M24LR64E-R 38/141 docid022712 rev 7 5.11 read operations read operations are performed independently of the state of the i2c_write_lock bit. after the successful completion of a read operat ion, the device?s internal address counter is incremented by one, to point to the next byte address. 5.12 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 11 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 5.13 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the byte addressed by the in ternal address counter. the counter is then incremented. the bus master terminates the tran sfer with a stop condition, as shown in figure 11 , without acknowledging the byte. 5.14 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next by te in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 11 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte ou tput. after the last memory address, the address counter ?rolls over?, and the device continues to output data from memory address 00h. 5.15 acknowledge in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the ninth bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its standby mode. docid022712 rev 7 39/141 M24LR64E-R i 2 c device operation 5.16 M24LR64E-R i 2 c password security the M24LR64E-R controls i 2 c sector write access using the 32-bit-long i 2 c password and the 64-bit i2c_write_lock bit area. the i 2 c password value is managed using two i 2 c commands: i 2 c present password and i 2 c write password. 5.16.1 i 2 c present password command description the i 2 c present password command is used in i 2 c mode to present the password to the M24LR64E-R in order to modify the write acce ss rights of all the memory sectors protected by the i2c_write_lock bits, including the pa ssword itself. if the presented password is correct, the access rights remain activated until the M24LR64E-R is powered off or until a new i 2 c present password command is issued. following a start condition, the bus master sends a device select code with the read/write bit (rw ) reset to 0 and the chip enable bit e2 at 1. the device acknowledges this, as shown in figure 12 , and waits for two i 2 c password address bytes, 09h and 00h. the device responds to each address byte with an acknowledge bit, and then waits for the four password data bytes, the validation code, 09h, and a resend of the four password data bytes. the most significant byte of the password is sent first, followed by the least significant bytes. it is necessary to send the 32-b it password twice to prevent any data corruption during the sequence. if the two 32-bit passwords sent are not exactly the same, the M24LR64E-R does not start the internal comparison. when the bus master generates a stop condit ion immediately after the ack bit (during the tenth bit time slot), an internal delay equival ent to the write cycle time is triggered. a stop condition at any other time does not trigger the internal delay. during that delay, the M24LR64E-R compares the 32 received data bits with the 32 bits of the stored i 2 c password. if the values match, the write access rights to all protected sectors are modified after the internal delay. if the values do not match, the protected se ctors remain protected. during the internal delay, the serial data (sda ) signal is disabled internally, and the device does not respond to any requests. figure 12. i 2 c present password command a i c 3 t a r t $ e v i c e s e l e c t c o d e 0 a s s w o r d a d d r e s s h 0 a s s w o r d a d d r e s s h 0 a s s w o r d ; = ! c k 2 7 ! c k ! c k ! c k $ e v i c e s e l e c t c o d e 0 a s s w o r d ; = 0 a s s w o r d ; = 0 a s s w o r d ; = ! c k ! c k ! c k ! c k g e n e r a t e d d u r i n g t h b i t t i m e s l o t 3 t o p 6 a l i d a t i o n c o d e h ! c k 0 a s s w o r d ; = ! c k 0 a s s w o r d ; = 0 a s s w o r d ; = 0 a s s w o r d ; = ! c k ! c k ! c k i 2 c device operation M24LR64E-R 40/141 docid022712 rev 7 5.16.2 i 2 c write password command description the i 2 c write password command is used to writ e a 32-bit block into the M24LR64E-R i 2 c password system area. this command is used in i 2 c mode to update the i 2 c password value. it cannot be used to update any of the rf passwords. after the write cycle, the new i 2 c password value is automatically activated. the i 2 c password value can only be modified after issuing a valid i 2 c present password command. on delivery, the i 2 c default password value is set to 0000 0000h and is activated. following a start condition, the bus master sends a device select code with the read/write bit (rw ) reset to 0 and the chip enable bit e2 at 1. the device acknowledges this, as shown in figure 13 , and waits for the two i 2 c password address bytes, 09h and 00h. the device responds to each address byte with an acknowledge bit, and then waits for the four password data bytes, the validation code, 07h, and a resend of the four password data bytes. the most significant byte of the password is sent first, followed by the least significant bytes. it is necessary to send twice the 32-bit password to prevent any data corruption during the write sequence. if the two 32-bit passwords sent are not exactly the same, the m24lr64e- r does not modify the i 2 c password value. when the bus master generates a stop condit ion immediately after the ack bit (during the tenth bit time slot), the internal write cycle is triggered. a stop condition at any other time does not trigger the internal write cycle. during the internal write cycle, the serial data (sda) signal is disabled internally, and the device does not respond to any requests. figure 13. i 2 c write password command a i b 3 t a r t $ e v i c e s e l e c t c o d e 0 a s s w o r d a d d r e s s h 0 a s s w o r d a d d r e s s h . e w p a s s w o r d ; = ! c k 2 7 ! c k ! c k ! c k $ e v i c e s e l e c t c o d e . e w p a s s w o r d ; = . e w p a s s w o r d ; = . e w p a s s w o r d ; = ! c k ! c k ! c k ! c k g e n e r a t e d d u r i n g t h b i t t i m e s l o t 3 t o p 6 a l i d a t i o n c o d e h ! c k . e w p a s s w o r d ; = ! c k . e w p a s s w o r d ; = . e w p a s s w o r d ; = . e w p a s s w o r d ; = ! c k ! c k ! c k docid022712 rev 7 41/141 M24LR64E-R M24LR64E-R memory initial state 6 M24LR64E-R memory initial state the device is delivered with all bits in the user memory array set to 1 (each byte contains ffh). the dsfid is programmed to ffh and the afi is programmed to 00h. configuration byte set to f4h: ? bit 7 to bit 4: all set to 1 ? bit 3: set to 0 (rf busy mode on rf wip/busy pin) ? bit 2: set to 1 (energy harvesting not activated by default) ? bit 1 and bit 0: set to 0 rf device operation M24LR64E-R 42/141 docid022712 rev 7 7 rf device operation the M24LR64E-R is divided into 64 sectors of 32 blocks of 32 bits, as shown in table 5 . each sector can be individually read- and/or write-protected using a specific lock or password command. read and write operations are possible if the addressed block is not protected. during a write, the 32 bits of the block are replaced by the new 32-bit value. the M24LR64E-R also has a 64-bit block that is used to store the 64-bit unique identifier (uid). the uid is compliant with the iso 15963 description, and its value is used during the anticollision sequence (inventory). this block is not accessible by the user in rf device operation and its value is writte n by st on the production line. the M24LR64E-R also includes an afi register in which the application family identifier is stored, and a dsfid register in which the da ta storage family identifier used in the anticollision algorithm is stored. the M24LR64E-R has three 32-bit blocks in wh ich the password codes are stored and an 8- bit configuration byte in which the ener gy harvesting mode and rf wip/busy pin configuration is stored. 7.1 rf communication and energy harvesting as the current consumption can affect the ac signal delivered by the antenna, rf communications with M24LR64E-R are not gu aranteed during voltage delivery on the energy harvesting analog output vout. rf communication can disturb and possibly stop energy harvesting mode. docid022712 rev 7 43/141 M24LR64E-R rf device operation 7.2 commands the M24LR64E-R supports the following commands: ? inventory , used to perform t he anticollision sequence. ? stay quiet , used to put the M24LR64E-R in quiet mode, where it does not respond to any inventory command. ? select , used to select the M24LR64E-R. af ter this command, the M24LR64E-R processes all read/write commands with select_flag set. ? reset to ready , used to put the M24LR64E-R in the ready state. ? read block , used to output the 32 bits of the selected block and its locking status. ? write block , used to write the 32-bit value in the selected block, provided that it is not locked. ? read multiple blocks , used to read the selected bl ocks and send back their value. ? write afi , used to write the 8-bit value in the afi register. ? lock afi , used to lock the afi register. ? write dsfid , used to write the 8-bit value in the dsfid register. ? lock dsfid , used to lock the dsfid register. ? get system info , used to provide the syst em information value. ? get multiple block security status , used to send the security status of the selected block. ? initiate , used to trigger the tag response to the inventory initiated sequence. ? inventory initiated , used to perform the anticollision sequence triggered by the initiate command. ? write-sector password , used to write the 32 bits of the selected password. ? lock-sector , used to write the sector security status bits of the selected sector. ? present-sector password , enables the user to present a password to unprotect the user blocks linked to this password. ? fast initiate , used to trigger the tag response to the inventory initiated sequence. ? fast inventory initiated , used to perform t he anticollision sequenc e triggered by the initiate command. ? fast read single block , used to output the 32 bits of the selected block and its locking status. ? fast read multiple blocks , used to read the selected blocks and send back their value. ? readcfg, used to read the 8-bit configuration byte and send back its value. ? writeehcfg , used to write the energy harvesting configuration bits into the configuration byte. ? writedocfg , used to write the rf wip/busy pin configuration bit into the configuration byte. ? setrstehen , used to set or reset the eh_enable bit into the volatile control register. ? checkehen , used to send back the value of the volatile control register. rf device operation M24LR64E-R 44/141 docid022712 rev 7 7.3 initial dialog for vicinity cards the dialog between the vicinity coupling device or vcd (commonly the ?rf reader?) and the vicinity integrated circuit card or vi cc (M24LR64E-R) takes place as follows: ? activation of the M24LR64E-R by the rf operating field of the vcd, ? transmission of a command by the vcd, ? transmission of a response by the M24LR64E-R. these operations use the rf power transfer and communication signal interface described below (see power transfer , frequency and operating field ). this technique is called rtf (reader talk first). 7.3.1 power transfer power is transferred to the M24LR64E-R by radio frequency at 13.56 mhz via coupling antennas in the M24LR64E-R and the vcd. the rf operating field of the vcd is transformed on the M24LR64E-R antenna to an ac voltage which is rectified, filtered and internally regulated. during communications, the amplitude modulation (ask) on this received signal is demodulated by the ask demodulator. 7.3.2 frequency the iso 15693 standard defines the carrier frequency ( f c ) of the operating field as 13.56 mhz 7 khz. 7.3.3 operating field the M24LR64E-R operates continuously betw een the minimum and maximum values of the electromagnetic field h defined in table 124 . the vcd has to generate a field within these limits. docid022712 rev 7 45/141 M24LR64E-R communication signal from vcd to M24LR64E-R 8 communication signal from vcd to M24LR64E-R communications between the vcd and the M24LR64E-R take place using the modulation principle of ask (amplitude shift keying). two modulation indexes are used, 10% and 100%. the M24LR64E-R decodes both. th e vcd determines which index is used. the modulation index is defined as [a ? b]/[a + b], where a is the peak signal amplitude, and b the minimum signal amplitude of the carrier frequency. depending on the choice made by the vcd, a ?pause? is created as described in figure 14 and figure 15 . the M24LR64E-R is operational for the 100% modulation index or for any degree of modulation index between 10% and 30% (see table 124 ). figure 14. 100% modulation waveform ?9 ??9 ?9 9 ??] ? u?o]? ? ? ? ? ? ? ? e d]v ~r? ? x ?x d? ~r? ?xee ex? x? dz o}l ? } ?? ?zoo }? ??]}vo (? ? ? e u? ]??? ? ? ? ? ? ? e communication signal from vcd to M24LR64E-R M24LR64E-R 46/141 docid022712 rev 7 figure 15. 10% mo dulation waveform table 19. 10% modulation parameters symbol parameter definition value hr 0.1 x (a ? b) max hf 0.1 x (a ? b) max dz s / ?zoo }? ??]}vo (}? v? o }( u}o?]}v ]v ? ? v v ?9x x r? d}o?]}v ]v ? z(u z? u ~r u? ? u? ~r ? z( ? z? ? ? ??] ? u?o]? d]v 9 z(u z? u ~r u? ? u? ~r z(u z? x ~r u? ? x? ~r z( ? z? ? ? ]??e ? ? ? ? ? ? ? ? ? ?x r? ? d? ?xee r? ex? r? ?9 docid022712 rev 7 47/141 M24LR64E-R data rate and data coding 9 data rate and data coding the data coding implemented in the m24lr64 e-r uses pulse position modulation. both data coding modes that are described in the iso15693 are supported by the M24LR64E-R. the selection is made by the vcd and indicated to the M24LR64E-R within the start of frame (sof). 9.1 data coding mode: 1 out of 256 the value of one single byte is represented by the position of one pause. the position of the pause on 1 of 256 successive time periods of 18.88 s (256/ f c ) determines the value of the byte. in this case, the transmission of one byte takes 4.833 ms and the resulting data rate is 1.65 kbits/s ( f c /8192). figure 16 illustrates this pulse position modulation te chnique. in this figu re, data e1h (225 decimal) is sent by the vcd to the M24LR64E-R. the pause occurs during the second half of the position of the time period that determines the value, as shown in figure 17 . a pause during the first period transmits the data value 00h. a pause during the last period transmits the data value ffh (255 decimal). figure 16. 1 out of 256 coding mode ! ) m s ? s ? s 0 u l s e - o d u l a t e d # a r r i e r data rate and data coding M24LR64E-R 48/141 docid022712 rev 7 figure 17. detail of a time period 9.2 data coding mode: 1 out of 4 the value of two bits is represented by the po sition of one pause. th e position of the pause on 1 of 4 successive time periods of 18.88 s (256/ f c ) determines the value of the two bits. four successive pairs of bits form a byte, where the least significant pair of bits is transmitted first. in this case, the transmission of one byte take s 302.08 s and the resulting data rate is 26.48 kbits/s ( f c /512). figure 18 illustrates the 1 out of 4 pu lse position technique and coding. figure 19 shows the transmission of e1h (225d - 1110 0001b) by the vcd. ! ) ? s ? s 0 u l s e - o d u l a t e d # a r r i e r 4 i m e 0 e r i o d o n e o f docid022712 rev 7 49/141 M24LR64E-R data rate and data coding figure 18. 1 out of 4 coding mode figure 19. 1 out of 4 coding example ! ) ? s ? s ? s ? s ? s ? s ? s ? s ? s ? s ? s ? s 0 u l s e p o s i t i o n f o r 0 u l s e p o s i t i o n f o r 0 u l s e p o s i t i o n f o r , 3 " 0 u l s e p o s i t i o n f o r , 3 " data rate and data coding M24LR64E-R 50/141 docid022712 rev 7 9.3 vcd to M24LR64E-R frames frames are delimited by a start of frame (sof) and an end of frame (eof). they are implemented using code viol ation. unused options are reserved for future use. the M24LR64E-R is ready to receive a new command frame from the vcd 311.5 s after sending a response frame to the vcd. the M24LR64E-R takes a power-up time of 0.1 ms after being activated by the powering field. after this delay, the M24LR64E-R is ready to receive a command frame from the vcd. 9.4 start of frame (sof) the sof defines the data coding mode the vcd is to use for the following command frame. the sof sequence described in figure 20 selects the 1 out of 256 data coding mode. the sof sequence described in figure 21 selects the 1 out of 4 data coding mode. the eof sequence for either coding mode is described in figure 22 . figure 20. sof to select 1 out of 256 data coding mode figure 21. sof to select 1 out of 4 data coding mode docid022712 rev 7 51/141 M24LR64E-R data rate and data coding figure 22. eof for either data coding mode communication signal from M24LR64E-R to vcd M24LR64E-R 52/141 docid022712 rev 7 10 communication signal from M24LR64E-R to vcd the M24LR64E-R has several modes defined for some parameters, so that it can operate in various noise environments and meet various application requirements. 10.1 load modulation the M24LR64E-R is capable of communicating to the vcd via an inductive coupling area whereby the carrier is loaded to generate a subcarrier with frequency f s . the subcarrier is generated by switching a load in the M24LR64E-R. the load-modulated amplitude received on th e vcd antenna must be of at least 10 mv when measured, as described in the test methods defined in international standard iso10373-7. 10.2 subcarrier the M24LR64E-R supports the one-subcarrier and two-subcarrier response formats. these formats are selected by the vcd using the fi rst bit in the protocol header. when one subcarrier is used, the frequency f s1 of the subcarrier load modulation is 423.75 khz ( f c /32). when two subcarriers are used, the frequency f s1 is 423.75 khz ( f c /32), and frequency f s2 is 484.28 khz ( f c /28). when using the two-subcarrier mode, the M24LR64E-R generates a continuous phase relationship between f s1 and f s2 . 10.3 data rates the M24LR64E-R can respond using the low or the high data rate format. the selection of the data rate is made by the vcd using the second bit in the protocol header. for fast commands, the selected data ra te is multiplied by two. table 20 shows the different data rates produced by the M24LR64E-R using the different response format combinations. table 20. response data rates data rate one subcarrier two subcarriers low standard commands 6.62 kbit/s ( f c /2048) 6.67 kbit/s ( f c /2032) fast commands 13.24 kbit/s ( f c /1024) not applicable high standard commands 26.48 kbit/s ( f c /512) 26.69 kbit/s ( f c /508) fast commands 52.97 kbit/s ( f c /256) not applicable docid022712 rev 7 53/141 M24LR64E-R bit representation and coding 11 bit representation and coding data bits are encoded using manchester codi ng, according to the following schemes. for the low data rate, same subcarri er frequency or frequencies is/are used. in this case, the number of pulses is multiplied by 4 and all times increase by this factor. for the fast commands using one subcarrier, all pulse numbers and times are divided by 2. 11.1 bit coding using one subcarrier 11.1.1 high data rate a logic 0 starts with eight pulses at 423.75 khz (f c /32) followed by an unmodulated time of 18.88 s, as shown in figure 23 . figure 23. logic 0, high data rate for the fast commands, a logic 0 starts with four pulses at 423.75 khz (f c /32) followed by an unmodulated time of 9.44 s, as shown in figure 24 . figure 24. logic 0, high data rate, fast commands a logic 1 starts with an unmodulated time of 18.8 8 s followed by eight pulses at 423.75 khz (f c /32), as shown in figure 25 . figure 25. logic 1, high data rate for the fast commands, a logic 1 starts with an unmodulated time of 9.44 s followed by four pulses of 423.75 khz (f c /32), as shown in figure 26 . figure 26. logic 1, high data rate, fast commands bit representation and coding M24LR64E-R 54/141 docid022712 rev 7 11.1.2 low data rate a logic 0 starts with 32 pulses at 423.75 khz (f c /32) followed by an unmodulated time of 75.52 s, as shown in figure 27 . figure 27. logic 0, low data rate for the fast commands, a logic 0 starts with 16 pulses at 423.75 khz (f c /32) followed by an unmodulated time of 37.76 s, as shown in figure 28 . figure 28. logic 0, low data rate, fast commands a logic 1 starts with an unmodulated time of 75. 52 s followed by 32 pulses at 423.75 khz (f c /32), as shown in figure 29 . figure 29. logic 1, low data rate for the fast commands, a logic 1 starts with an unmodulated time of 37.76 s followed by 16 pulses at 423.75 khz (f c /32), as shown in figure 30 . figure 30. logic 1, low data rate, fast commands ?x?? r? ]?? ?x?? r? ]? docid022712 rev 7 55/141 M24LR64E-R bit representation and coding 11.2 bit coding using two subcarriers 11.2.1 high data rate a logic 0 starts with eight pulses at 423.75 khz (f c /32) followed by nine pulses at 484.28 khz (f c /28), as shown in figure 31 . bit coding using two subcarriers is not supported for the fast commands. figure 31. logic 0, high data rate a logic 1 starts with nine pulses at 484.28 khz (f c /28) followed by eight pulses at 423.75 khz (f c /32), as shown in figure 32 . bit coding using two subcarriers is not supported for the fast commands. figure 32. logic 1, high data rate 11.2.2 low data rate a logic 0 starts with 32 pulses at 423.75 khz (f c /32) followed by 36 pulses at 484.28 khz (f c /28), as shown in figure 33 . bit coding using two subcarriers is not supported for the fast commands. figure 33. logic 0, low data rate a logic 1 starts with 36 pulses at 484.28 khz (f c /28) followed by 32 pulses at 423.75 khz (f c /32) as shown in figure 34 . bit coding using two subcarriers is not supported for the fast commands. figure 34. logic 1, low data rate ?xe r? ]?e ?xe r? ]?? M24LR64E-R to vcd frames M24LR64E-R 56/141 docid022712 rev 7 12 M24LR64E-R to vcd frames frames are delimited by an sof and an eof. they are implemented using code violation. unused options are reserved for future use. for the low data rate, the same subcarrier frequency or frequencies is/are used. in this ca se, the number of pulses is multiplied by 4. for the fast commands using one subcarrier, all pulse numbers and times are divided by 2. 12.1 sof when using one subcarrier 12.1.1 high data rate the sof includes an unmodulated time of 56.64 s, followed by 24 pulses at 423.75 khz (f c /32), and a logic 1 that consists of an unmo dulated time of 18.88 s followed by eight pulses at 423.75 khz, as shown in figure 35 . figure 35. start of frame, high data rate, one subcarrier for the fast commands, the sof comprises an unmodulated time of 28.32 s, followed by 12 pulses at 423.75 khz (f c /32), and a logic 1 that consists of an unmodulated time of 9.44 s followed by four pulses at 423.75 khz, as shown in figure 36 . figure 36. start of frame, high data rate, one subcarrier, fast commands 12.1.2 low data rate the sof comprises an unmodulated time of 22 6.56 s, followed by 96 pulses at 423.75 khz ( f c /32), and a logic 1 that consists of an unmodulated time of 75.52 s followed by 32 pulses at 423.75 khz, as shown in figure 37 . figure 37. start of frame, low data rate, one subcarrier ?xe r? ]?? ?x?? r? e??x? r? ]?? ?xe r? docid022712 rev 7 57/141 M24LR64E-R M24LR64E-R to vcd frames for the fast commands, the sof comprises an unmodulated time of 113.28 s, followed by 48 pulses at 423.75 khz ( f c /32), and a logic 1 that includes an unmodulated time of 37.76 s followed by 16 pulses at 423.75 khz, as shown in figure 38 . figure 38. start of frame, low data rate, one subcarrier, fast commands 12.2 sof when using two subcarriers 12.2.1 high data rate the sof comprises 27 pulses at 484.28 khz ( f c /28), followed by 24 pulses at 423.75 khz ( f c /32), and a logic 1 that includes nine pulses at 484.28 khz followed by eight pulses at 423.75 khz, as shown in figure 39 . bit coding using two subcarriers is not supported for the fast commands. figure 39. start of frame, high data rate, two subcarriers 12.2.2 low data rate the sof comprises 108 pulses at 484.28 khz ( f c /28), followed by 96 pulses at 423.75 khz ( f c /32), and a logic 1 that includes 36 pulses at 484.28 khz followed by 32 pulses at 423.75 khz, as shown in figure 40 . bit coding using two subcarriers is not supported for the fast commands. figure 40. start of frame, low data rate, two subcarriers ?x?? r? ]??? ?xe r? ee?x? r? ]??? e?x?e r? M24LR64E-R to vcd frames M24LR64E-R 58/141 docid022712 rev 7 12.3 eof when using one subcarrier 12.3.1 high data rate the eof comprises a logic 0 that includes eight pulses at 423.75 khz and an unmodulated time of 18.88 s, followed by 24 pulses at 423.75 khz ( f c /32), and by an unmodulated time of 56.64 s, as shown in figure 41 . figure 41. end of frame, high data rate, one subcarrier for the fast commands, the eof comprises a logic 0 that includes four pulses at 423.75 khz and an unmodulated time of 9.44 s, followed by 12 pulses at 423.75 khz ( f c /32) and an unmodulated time of 37.76 s, as shown in figure 42 . figure 42. end of frame, high data rate, one subcarrier, fast commands 12.3.2 low data rate the eof comprises a logic 0 that includes 32 pulses at 423.75 khz and an unmodulated time of 75.52 s, followed by 96 pulses at 423.75 khz ( f c /32) and an unmodulated time of 226.56 s, as shown in figure 43 . figure 43. end of frame, low data rate, one subcarrier for the fast commands, the eof comprises a logi c 0 that includes 16 pulses at 423.75 khz and an unmodulated time of 37.76 s, followed by 48 pulses at 423.75 khz ( f c /32) and an unmodulated time of 113.28 s, as shown in figure 44 . figure 44. end of frame, low data rate, one subcarrier, fast commands docid022712 rev 7 59/141 M24LR64E-R M24LR64E-R to vcd frames 12.4 eof when using two subcarriers 12.4.1 high data rate the eof comprises a logic 0 that includes eigh t pulses at 423.75 khz and nine pulses at 484.28 khz, followed by 24 pulses at 423.75 khz ( f c /32) and 27 pulses at 484.28 khz ( f c /28), as shown in figure 45 . bit coding using two subcarriers is not supported for the fast commands. figure 45. end of frame, high data rate, two subcarriers 12.4.2 low data rate the eof comprises a logic 0 that includes 32 pulses at 423.75 khz and 36 pulses at 484.28 khz, followed by 96 pulses at 423.75 khz ( f c /32) and 108 pulses at 484.28 khz ( f c /28), as shown in figure 46 . bit coding using two subcarriers is not supported for the fast commands. figure 46. end of frame, low data rate, two subcarriers ?x?? r? ]??? ?xe r? ee?x? r? ]??? e?x?e r? unique identifier (uid) M24LR64E-R 60/141 docid022712 rev 7 13 unique identifier (uid) the M24LR64E-R is uniquely identified by a 64-bit unique identifi er (uid). this uid complies with iso/iec 15963 and iso/iec 7816-6. the uid is a read-only code and comprises: ? eight msbs with a value of e0h, ? the ic manufacturer code ?st 02h? on 8 bits (iso/iec 7816-6/am1), ? a unique serial number on 48 bits. with the uid, each M24LR64E-R can be addressed uniquely and individually during the anticollision loop and for on e-to-one exchanges between a vcd and an M24LR64E-R. table 21. uid format msb lsb 63 56 55 48 47 0 0xe0 0x02 unique serial number docid022712 rev 7 61/141 M24LR64E-R application family identifier (afi) 14 application family identifier (afi) the afi (application family identifier) represents the type of application targeted by the vcd and is used to identify, among all the m24l r64e-rs present, only those that meet the required applic ation criteria. figure 47. M24LR64E-R decision tree for afi the afi is programmed by the M24LR64E-R issuer (or purchaser) in the afi register. once programmed and locked, it can no longer be modified. the most significant nibble of the afi is used to code one specific or all application families. the least significant nibble of the afi is us ed to code one specific or all application subfamilies. subfamily codes diff erent from 0 ar e proprietary. (see iso 15693-3 documentation.) ! ) ) n v e n t o r y r e q u e s t r e c e i v e d . o . o a n s w e r 9 e s . o ! & ) v a l u e 9 e s . o ! & ) f l a g s e t 9 e s ! n s w e r g i v e n b y t h e - 2 & t o t h e ) n v e n t o r y r e q u e s t ! & ) v a l u e ) n t e r n a l v a l u e data storage format identifier (dsfid) M24LR64E-R 62/141 docid022712 rev 7 15 data storage format identifier (dsfid) the data storage format identifier indicates how the data is structured in the M24LR64E-R memory. the logical organization of data can be known instantly using the dsfid. it can be programmed and locked using the write dsfid and lock dsfid commands. 15.1 crc the crc used in the M24LR64E-R is calculated as per the definition in iso/iec 13239. the initial register contents are all ones: ?ffff?. the two-byte crc is appended to each request and response, within each frame, before the eof. the crc is calculated on all the bytes after the sof up to the crc field. upon reception of a request from the vcd, th e M24LR64E-R verifies that the crc value is valid. if it is invalid, the M24LR64E-R discards the frame and does not answer the vcd. upon reception of a response from the M24LR64E-R, it is recommended that the vcd verifies whether the crc value is valid. if it is invalid, actions to be performed are left to the discretion of the vcd designer. the crc is transmitted least significant byte firs t. each byte is transm itted least significant bit first. table 22. crc transmission rules lsbyte lsbyte lsbitmsbitlsbitmsbit crc 16 (8 bits) crc 16 (8 bits) docid022712 rev 7 63/141 M24LR64E-R M24LR64E-R protocol description 16 M24LR64E-R protocol description the transmission protocol (or simply ?the protocol?) defines the mechanism used to exchange instructions and data between the vcd and the M24LR64E-R in both directions. it is based on the concept of ?vcd talks first?. this means that an M24LR64E-R does not st art transmitting unless it has received and properly decoded an instruction sent by the vcd. the protocol is based on an exchange of: ? a request from the vcd to the M24LR64E-R, ? a response from the M24LR64E-R to the vcd. each request and each response are contained in a frame. the frame delimiters (sof, eof) are described in section 12 . each request consists of: ? a request sof (see figure 20 and figure 21 ), ? flags, ? a command code, ? parameters depending on the command, ? application data, ? a 2-byte crc, ? a request eof (see figure 22 ). each response consists of: ? an answer sof (see figure 35 to figure 40 ), ? flags, ? parameters depending on the command, ? application data, ? a 2-byte crc, ? an answer eof (see figure 41 to figure 46 ). the protocol is bit-oriented. the number of bits transmitted in a frame is a multiple of eight (8), that is an inte ger number of bytes. a single-byte field is transmitted least signific ant bit (lsbit) first. a multiple-byte field is transmitted least significant byte (lsbyte) first and each byte is transmitted least significant bit (lsbit) first. the setting of the flags indicates the presence of the optional fields. when the flag is set (to one), the field is present. when the flag is reset (to zero), the field is absent. table 23. vcd request frame format request sof request_flags command code parameters data 2-byte crc request eof table 24. M24LR64E-R response frame format response sof response_flags parameters data 2-byte crc response eof M24LR64E-R protocol description M24LR64E-R 64/141 docid022712 rev 7 figure 48. M24LR64E-R protocol timing vcd request frame ( table 23 ) request frame ( table 23 ) m24lr64 e-r response frame ( table 24 ) response frame ( table 24 ) timing <-t 1 -> <-t 2 -> <-t 1 -> <-t 2 -> docid022712 rev 7 65/141 M24LR64E-R M24LR64E-R states 17 M24LR64E-R states an M24LR64E-R can be in one of four states: ? power-off ? ready ? quiet ? selected transitions between these states are specified in figure 49 and table 25 . 17.1 power-off state the M24LR64E-R is in the power-off state when it does not receive enough energy from the vcd. 17.2 ready state the M24LR64E-R is in the ready state when it receives enough energy from the vcd. when in the ready state, the M24LR64E-R ans wers any request where the select_flag is not set. 17.3 quiet state when in the quiet state, the M24LR64E-R answers any request except for inventory requests with the address_flag set. 17.4 selected state in the selected state, the M24LR64E-R answers any request in all modes (see section 18 ): ? request in select mode with the select_flag set ? request in addressed mode if the uid matches ? request in non-addressed mode as it is the mode for general requests M24LR64E-R states M24LR64E-R 66/141 docid022712 rev 7 figure 49. M24LR64E-R state transition diagram 1. the M24LR64E-R returns to the power off state if the tag is out of the rf field for at least t rf_off . please refer to application note an4125 for more information. 2. the intention of the state transition method is that only one M24LR64E-R should be in the selected state at a time. table 25. M24LR64E-R response depending on request_flags flags address_flag select_flag 1 addressed 0 non addressed 1 selected 0 non selected M24LR64E-R in ready or selected state (devices in quiet state do not answer) -x-x M24LR64E-R in selected state - x x - M24LR64E-R in ready, quiet or selected state (the device which matches the uid) x- -x error (03h) x - x - $ , e 3 r z h u r i i , q i l h o g 2 x w r i i l h o g 5 h d g \ 4 x l h w 6 h o h f w h g $ q \ r w k h u & r p p d q g z k h u h 6 h o h f w b ) o d j l v q r w v h w 6 w d \ t x l h w 8 , ' 6 h o h f w 8 , ' $ q \ r w k h u f r p p d q g $ q \ r w k h u f r p p d q g z k h u h w k h $ g g u h v v b ) o d j l v v h w $ 1 ' z k h u h , q y h q w r u \ b ) o d j l v q r w v h w 6 w d \ t x l h w 8 , ' 6 h o h f w 8 , ' 5 h v h w w r u h d g \ z k h u h 6 h o h f w b ) o d j l v v h w r u 6 h o h f w g l i i h u h q w 8 , ' 5 h v h w w r u h d g \ 2 x w r i 5 ) i l h o g d i w h u w 5 ) b 2 ) ) 2 x w r i 5 ) i l h o g d i w h u w 5 ) b 2 ) ) d i w h u w 5 ) b 2 ) ) docid022712 rev 7 67/141 M24LR64E-R modes 18 modes the term ?mode? refers to the mechanism used in a request to specify the set of M24LR64E-Rs that answers the request. 18.1 addressed mode when the address_flag is set to 1 (addressed mode), the request contains the unique id (uid) of the addressed M24LR64E-R. any M24LR64E-R that receives a request with the address_flag set to 1 compares the received unique id to its own. if it matches, then the M24LR64E-R executes the request (if possible) and returns a response to the vcd as specified in the command description. if the uid does not match, then it remains silent. 18.2 non-addressed mode (general request) when the address_flag is cleared to 0 (non-addressed mode), the request does not contain a unique id. any M24LR64E-R receiving a request with the address_flag cleared to 0 executes it and returns a response to the vcd as specified in the command description. 18.3 select mode when the select_flag is set to 1 (select mode ), the request does not contain an m24lr64e- r unique id. the M24LR64E-R in the selected state that receives a request with the select_flag set to 1 executes it and returns a response to the vcd as specified in the command description. only M24LR64E-Rs in the selected state answer a request where the select_flag is set to 1. the system design ensures in theory that only one M24LR64E-R can be in the select state at a time. request format M24LR64E-R 68/141 docid022712 rev 7 19 request format the request consists of: ? an sof, ? flags, ? a command code, ? parameters and data, ? a crc, ? an eof. 19.1 request flags in a request, the ?flags? field specifies the ac tions to be performed by the M24LR64E-R and whether corresponding fields are present or not. the flags field consists of eight bits. bit 3 (i nventory_flag) of the request flag defines the contents of the four msbs (bit s 5 to 8). when bit 3 is reset (0), bits 5 to 8 define the M24LR64E-R selection criteria. when bit 3 is set (1), bits 5 to 8 define the M24LR64E-R inventory parameters. table 26. general request format s o f request_flags command code parameters data crc e o f table 27. definition of request flags 1 to 4 bit no flag level description bit 1 subcarrier_flag (1) 1. subcarrier_flag refers to th e M24LR64E-R-to-vcd communication. 0 a single subcarrier frequency is used by the M24LR64E-R 1 two subcarriers are used by the M24LR64E-R bit 2 data_rate_flag (2) 2. data_rate_flag refers to the M24LR64E-R-to-vcd communication. 0 low data rate is used 1 high data rate is used bit 3 inventory_flag 0 the meaning of flags 5 to 8 is described in ta ble 28 1 the meaning of flags 5 to 8 is described in ta ble 29 bit 4 protocol_extension_flag (3) 3. protocol_extension_flag must be set to 1 for re ad single block, read multiple block, fast read multiple block, write single block, and get multiple block secu rity status commands. get system info command supports two options: a standard response format when protocol_extension_flag is set to 0, and a rich response when protocol extension is set to 1. 0 no protocol format extension 1 protocol format extension docid022712 rev 7 69/141 M24LR64E-R request format . table 28. request flags 5 to 8 when bit 3 = 0 bit nb flag level description bit 5 select flag (1) 1. if the select_flag is set to 1, the address_flag is set to 0 and the uid fi eld is not present in the request. 0 the request is executed by any M24LR64E-R according to the setting of address_flag 1 the request is executed only by the M24LR64E-R in selected state bit 6 address flag (1) 0 the request is not addressed. uid fi eld is not present. the request is executed by all M24LR64E-Rs. 1 the request is addressed. uid field is present. the request is executed only by the M24LR64E-R whose uid matches the uid specified in the request. bit 7 option flag 0 option not activated. 1 option activated. bit 8 rfu 0 - table 29. request flags 5 to 8 when bit 3 = 1 bit nb flag level description bit 5 afi flag 0 afi field is not present 1 afi field is present bit 6 nb_slots flag 0 16 slots 11 slot bit 7 option flag 0 - bit 8 rfu 0 - response format M24LR64E-R 70/141 docid022712 rev 7 20 response format the response consists of: ? an sof, ? flags, ? parameters and data, ? a crc, ? an eof. 20.1 response flags in a response, the flags indicate how actions have been performed by the M24LR64E-R and whether corresponding fields are present or not. the response flags consist of eight bits. table 30. general response format s o f response_flags parameters data crc e o f table 31. definitions of response flags 1 to 8 bit nb flag level description bit 1 error_flag 0 no error 1 error detected. error code is in the ?error? field. bit 2 rfu 0 - bit 3 rfu 0 - bit 4 extension flag 0 no extension bit 5 rfu 0 - bit 6 rfu 0 - bit 7 rfu 0 - bit 8 rfu 0 - docid022712 rev 7 71/141 M24LR64E-R response format 20.2 response error code if the error_flag is set by the M24LR64E-R in the response, the error code field is present and provides information about the error that occurred. error codes not specified in table 32 are reserved for future use. table 32. response error code definition error code meaning 03h the option is not supported. 0fh error with no information given. 10h the specified block is not available. 11h the specified block is already locked and thus cannot be locked again. 12h the specified block is locked and its contents cannot be changed. 13h the specified block was not successfully programmed. 14h the specified block wa s not successfully locked. 15h the specified block is read-protected. anticollision M24LR64E-R 72/141 docid022712 rev 7 21 anticollision the purpose of th e anticollision sequence is to invent ory the M24LR64E-Rs present in the vcd field using their unique id (uid). the vcd is the master of communications with one or several M24LR64E-Rs. it initiates an M24LR64E-R communication by issuing the inventory request. the M24LR64E-R sends its response in the determined slot or does not respond. 21.1 request parameters when issuing the inventory command: ? the vcd sets the nb_slots_flag as desired. ? the vcd adds the mask length and the mask value after the command field: ? the mask length is the number of significant bits of the mask value. ? the mask value is contained in an integer number of bytes. the mask length indicates the number of significant bits. lsb is transmitted first. ? if the mask length is not a multiple of 8 (bits), as many 0-bits as required are added to the mask value msb, so that the mask valu e is contained in an integer number of bytes. ? the next field starts at the next byte boundary. in the example provided in table 34 and figure 50 , the mask length is 11 bits. five 0-bits are added to the mask value msb. the 11-bit mask and the current slot number are compared to the uid. table 33. inventory request format msb lsb sof request_flags command optional afi mask length mask value crc eof - 8 bits 8 bits 8 bits 8 bits 0 to 8 bytes 16 bits - table 34. example of the addition of 0-bits to an 11-bit mask value msb (b 15 )lsb (b 0 ) 0000 0 100 1100 1111 0-bits added 11-bit mask value docid022712 rev 7 73/141 M24LR64E-R anticollision figure 50. principle of comparison between the mask, the slot number and the uid the afi field is present if the afi_flag is set. the pulse is generated according to the de finition of the eof in iso/iec 15693-2. the first slot starts immediately after the reques t eof is received. to switch to the next slot, the vcd sends an eof. the following rules and restrictions apply: ? if no M24LR64E-R answer is detected, the v cd may switch to the next slot by sending an eof. ? if one or more M24LR64E-R answers are detected, the vcd waits until the complete frame has been received before sending an eof for switching to the next slot. ! ) - a s k v a l u e r e c e i v e d i n t h e ) n v e n t o r y c o m m a n d b b i t s 4 h e - a s k v a l u e l e s s t h e p a d d i n g s i s l o a d e d i n t o t h e 4 a g c o m p a r a t o r b b i t s 4 h e 3 l o t c o u n t e r i s c a l c u l a t e d x x x x . b ? s l o t s ? f l a g s s l o t s 3 l o t # o u n t e r i s b i t s 4 h e 3 l o t c o u n t e r i s c o n c a t e n e d t o t h e - a s k v a l u e x x x x b . b ? s l o t s ? f l a g s b i t s 4 h e c o n c a t e n a t e d r e s u l t i s c o m p a r e d w i t h t h e l e a s t s i g n i f i c a n t b i t s o f t h e 4 a g 5 ) $ x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x b i t s , 3 " - 3 " b , 3 " - 3 " , 3 " - 3 " , 3 " - 3 " b b # o m p a r e " i t s i g n o r e d 5 ) $ b i t s request processing by the M24LR64E-R M24LR64E-R 74/141 docid022712 rev 7 22 request processing by the M24LR64E-R upon reception of a valid request, the M24LR64E-R performs the following algorithm: ? nbs is the total number of slots (1 or 16) ? sn is the current slot number (0 to 15) ? lsb (value, n) function returns the n less significant bits of value ? msb (value, n) function returns the n most significant bits of value ? ?&? is the concatenation operator ? slot_frame is either an sof or an eof sn = 0 if (nb_slots_flag) then nbs = 1 sn_length = 0 endif else nbs = 16 sn_length = 4 endif label1: if lsb(uid, sn_length + mask_length) = lsb(sn,sn_length)&lsb(mask,mask_length) then answer to inventory request endif wait (slot_frame) if slot_frame = sof then stop anticollision decode/process request exit endif if slot_frame = eof if sn < nbs-1 then sn = sn + 1 goto label1 exit endif endif docid022712 rev 7 75/141 M24LR64E-R explanation of the possible cases 23 explanation of the possible cases figure 51 summarizes the main po ssible cases that can oc cur during an anticollision sequence when the number of slots is 16. the sequence of steps is as follows: ? the vcd sends an inventory request, in a frame terminated by an eof. the number of slots is 16. ? M24LR64E-R_1 transmits its response in slot 0. it is the only one to do so, therefore no collision occurs and its uid is re ceived and registered by the vcd. ? the vcd sends an eof in order to switch to the next slot. ? in slot 1, two M24LR64E-Rs (M24LR64E-R_2 and M24LR64E-R_3) transmit a response, thus generating a collision. the v cd records the event an d registers that a collision was detected in slot 1. ? the vcd sends an eof in order to switch to the next slot. ? in slot 2, no M24LR64E-R transmits a response. therefore the vcd does not detect any M24LR64E-R sof and switches to the next slot by sending an eof. ? in slot 3, another collision occurs d ue to responses from M24LR64E-R_4 and M24LR64E-R_5. ? the vcd sends a request (for instance a read block) to M24LR64E-R_1 whose uid has already been correctly received. ? all M24LR64E-Rs detect an so f and exit the anti collision sequence. they process this request and since the request is addres sed to M24LR64E-R_1, only M24LR64E-R_1 transmits a response. ? all M24LR64E-Rs are ready to receive another request. if it is an inventory command, the slot numbering sequence restarts from 0. note: the decision to in terrupt the anticollision s equence is made by the vcd. eofs could have been sent until slot 16, and the request to M24LR64E-R_1 sent then. explanation of the possible cases M24LR64E-R 76/141 docid022712 rev 7 figure 51. description of a possible antico llision sequence ! ) 3 l o t 3 l o t 3 l o t 3 l o t 6 # $ 3 / & ) n v e n t o r y 2 e q u e s t % / & % / & % / & % / & 3 / & 2 e q u e s t t o - 2 & ? % / & 2 e s p o n s e 2 e s p o n s e - 2 & s 2 e s p o n s e f r o m - 2 & ? 2 e s p o n s e 2 e s p o n s e 2 e s p o n s e 4 i m i n g t t t t t t t t # o m m e n t . o c o l l i s i o n # o l l i s i o n . o 2 e s p o n s e # o l l i s i o n 4 i m e docid022712 rev 7 77/141 M24LR64E-R inventory initiated command 24 inventory initiated command the M24LR64E-R provides a special feature to improve the inventory time response of moving tags using the initiate_f lag value. this flag, controlle d by the initiate command, allows tags to answer inventory initiated commands. for applications in which multiple tags are moving in front of a reader, it is possible to miss tags using the standard inventory command. the reason is that the inventory sequence has to be performed on a global tree search. for example, a tag with a particular uid value may have to wait the run of a long tree search before being inventoried. if the delay is too long, the tag may be out of the field before it has been detected. using the initiate command, the inventory sequ ence is optimized. wh en multiple tags are moving in front of a reader, the ones which are within the reader field are initiated by the initiate command. in this case, a small batch of tags answers to the inventory initiated command, which optimizes the time necessary to identify all the tags. when finished, the reader has to issue a new initiate command in order to initiate a new small batch of tags which are new inside the reader field. it is also possible to reduce the inventory sequence time using the fast initiate and fast inventory initiated commands. these commands allow the M24LR64E-Rs to increase their response data rate by a factor of 2, up to 53 kbit/s. timing definition M24LR64E-R 78/141 docid022712 rev 7 25 timing definition 25.1 t 1 : M24LR64E-R response delay upon detection of the rising edge of the eof received from the vcd, the M24LR64E-R waits for a t 1nom time before transmitting its response to a vcd request or switching to the next slot during an inventory process. values of t 1 are given in table 35 . the eof is defined in figure 22 . 25.2 t 2 : vcd new request delay t 2 is the time after which the vcd may send an eof to switch to the next slot when one or more M24LR64E-R responses have been received during an inventory command. it starts from the reception of the eof from the M24LR64E-Rs. the eof sent by the vcd may be either 10% or 100% modulated regardless of the modulation index used for transmitting the vcd request to the M24LR64E-R. t 2 is also the time after which the vcd may send a new request to the M24LR64E-R, as described in figure 48 . values of t 2 are given in table 35 . 25.3 t 3 : vcd new request delay when no response is received from the M24LR64E-R t 3 is the time after which the vcd may send an eof to switch to the next slot when no M24LR64E-R response has been received. the eof sent by the vcd may be either 10% or 100% modulated regardless of the modulation index used for transmitting the vcd request to the M24LR64E-R. from the time the vcd has generated the rising edge of an eof: ? if this eof is 100% modulated, the v cd waits for a time at least equal to t 3min before sending a new eof. ? if this eof is 10% modulated, the vcd wait s for a time at least equal to the sum of t 3min + the M24LR64E-R nominal response time (which depends on the M24LR64E-R data rate and subcarrier modulation mode) before sending a new eof. table 35. timing values (1) 1. the tolerance of specific timings is 32/fc. minimum (min) values n ominal (nom) values maximum (max) values t 1 318.6 s 320.9 s 323.3 s t 2 309.2 s no t nom no t max t 3 t 1max (2) + t sof (3) 2. t 1max does not apply for write-alike requests. ti ming conditions for write-alike requests are defined in the command description. 3. t sof is the time taken by the M24LR64E-R to transmit an sof to the vcd. t sof depends on the current data rate: high data rate or low data rate. no t nom no t max docid022712 rev 7 79/141 M24LR64E-R command codes 26 command codes the M24LR64E-R supports the commands described in this section. their codes are given in table 36 . - table 36. command codes command code standard function command code custom function 01h inventory 2ch get multiple block security status 02h stay quiet b1h write-sector password 20h read single block b2h lock-sector 21h write single block b3h present-sector password 23h read multiple block c0h fast read single block 25h select c1h fast inventory initiated 26h reset to ready c2h fast initiate 27h write afi c3h fast read multiple block 28h lock afi d1h inventory initiated 29h write dsfid d2h initiate 2ah lock dsfid a0h readcfg 2bh get system info a1h writeehcfg - - a2h setrstehen - - a3h checkehen -- a4hwritedocfg command codes M24LR64E-R 80/141 docid022712 rev 7 26.1 inventory when receiving the inventory request, the M24LR64E-R runs the anticollision sequence. the inventory_flag is set to 1. the meaning of flags 5 to 8 is shown in table 29 . the request contains: ? the flags, ? the inventory command code (see table 36 ), ? the afi if the afi flag is set, ? the mask length, ? the mask value, ? the crc. the M24LR64E-R does not generate any answer in case of error. the response contains: ? the flags, ? the unique id. during an inventory process, if the vcd does not receive an rf M24LR64E-R response, it waits for a time t 3 before sending an eof to switch to the next slot. t 3 starts from the rising edge of the request eof sent by the vcd. ? if the vcd sends a 100% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t sof ? if the vcd sends a 10% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t nrt where: ? t sof is the time required by the m24lr 64e-r to transmit an sof to the vcd, ? t nrt is the nominal response time of the M24LR64E-R. t nrt and t sof are dependent on the M24LR64E-R-to-vcd data rate and subcarrier modulation mode. when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof starting the inventory command to the end of the M24LR64E-R response. if the m24lr64e- r does not receive the corresponding slot marker, the rf wip/busy pin remains at 0 until the next rf power-off. table 37. inventory request format request sof request_flag s inventory optional afi mask length mask value crc16 request eof - 8 bits 01h 8 bits 8 bits 0 - 64 bits 16 bits - table 38. inventory response format response sof response_flags dsfid uid crc16 response eof - 8 bits 8 bits 64 bits 16 bits - docid022712 rev 7 81/141 M24LR64E-R command codes when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. figure 52. m24lr64e rf-busy management following inventory command 0 6 9 6 2 ) , q y h q w r u \ f r p p d q g ( 2 ) ( 2 ) 6 o r w 6 2 ) , u h s o \ 0 / 5 [ ( 2 ) ( 2 ) ( 2 ) 6 o r w q 0 / 5 [ u h s o l h v l q v o r w q 5 ) b % x v \ l v u h o h d v h g d i w h u 0 / 5 [ u h v s r q v h 5 ) b % x v \ 6 2 ) , q y h q w r u \ f r p p d q g ( 2 ) ( 2 ) 6 o r w ( 2 ) 6 o r w q 6 o r w q q h y h u r f f x u v 5 ) b % x v \ l v r q o \ u h o h d v h g e \ 3 r z h u r i i 3 r z h u r i i 5 ) b % x v \ 6 2 ) , q y h q w r u \ f r p p d q g ( 2 ) ( 2 ) 6 o r w 9 & ' v h q g v d 9 d o l g f r p p d q g e h i r u h v o r w q 5 ) b % x v \ l v u h o h d v h g d i w h u 0 / 5 [ u h v s r q v h 5 ) b % x v \ 6 2 ) , q y h q w r u \ f r p p d q g ( 2 ) ( 2 ) 6 o r w 9 & ' v h q g v d % d g f r p p d q g e h i r u h v o r w q 5 ) b % x v \ l v u h o h d v h g d i w h u 9 & ' f r p p d q g 5 ) b % x v \ 6 2 ) , 1 h z f r p p d q g ( 2 ) 6 2 ) , u h s o \ 0 / 5 [ ( 2 ) 6 2 ) , 1 h z f r p p d q g ( 2 ) command codes M24LR64E-R 82/141 docid022712 rev 7 26.2 stay quiet command code = 0x02 on receiving the stay quiet command, the M24LR64E-R enters the quiet state if no error occurs, and does not send back a response. there is no response to the stay quiet command even if an error occurs. when in the quiet state: ? the M24LR64E-R does not process any r equest if the inventory_flag is set, ? the M24LR64E-R processes any addressed request. the M24LR64E-R exits the quiet state when: ? it is reset (power off), ? receiving a select request. it t hen goes to the selected state, ? receiving a reset to ready request. it then goes to the ready state. the stay quiet command must always be executed in addressed mode (select_flag is reset to 0 and address_flag is set to 1). when configured in the rf busy mode, the rf wip/busy pin is tied to 0 during the stay quiet command. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. table 39. stay quiet request format request sof request flags stay quiet uid crc16 request eof - 8 bits 02h 64 bits 16 bits - figure 53. stay quiet frame exchange between vcd and M24LR64E-R vcd sof stay quiet request eof M24LR64E-R timing docid022712 rev 7 83/141 M24LR64E-R command codes 26.3 read single block on receiving the read single block command, the M24LR64E-R reads the requested block and sends back its 32-bit value in the respon se. the protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. if the protocol_extension_flag is at 0, the M24LR64E-R answers with an error co de. the option_flag is supported. request parameters: ? request flags ? uid (optional) ? block number response parameters: ? sector security status if option_flag is set (see table 42 ) ? four bytes of block data response parameter: ? error code as error_flag is set ? 10h: the specified block is not available ? 15h: the specified block is read-protected table 40. read single block request format request sof request_flags read single block uid (1) 1. gray color means that the field is optional. block number crc16 request eof -8 bits 20h 64 bits 16 bits 16 bits - table 41. read single block response format when error_flag is not set response sof response_flags sector security status (1) 1. gray color means that the field is optional. data crc16 response eof -8 bits 8 bits 32 bits 16 bits - table 42. sector security status b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved for future use. all at 0. password control bits read / write protection bits 0: current sector not locked 1: current sector locked table 43. read single block response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - command codes M24LR64E-R 84/141 docid022712 rev 7 when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the read single block command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. 26.4 write single block on receiving the write single block command, the M24LR64E-R writes the data contained in the request to the requested block and reports whether the write operation was successful in the response. the protocol_ext ension_flag should be set to 1 for the M24LR64E-R to operate correctly. if the pr otocol_extension_flag is at 0, the M24LR64E-R answers with an error code. the option_flag is supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%), otherwise the M24LR64E-R may not program correctly the data into the memory. the w t time is equal to t 1nom + 18 302 s. request parameters: ? request flags ? uid (optional) ? block number ? data response parameter: ? no parameter. the response is sent back after the writing cycle. figure 54. read single block frame exchange between vcd and M24LR64E-R vcd sof read single block request eof M24LR64E-R <-t 1 -> sof read single block response eof table 44. write single block request format request sof request_flags write single block uid (1) 1. gray color means that the field is optional. block number data crc16 request eof - 8 bits 21h 64 bits 16 bits 32 bits 16 bits - table 45. write single block response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - docid022712 rev 7 85/141 M24LR64E-R command codes response parameter: ? error code as error_flag is set: ? 0fh: error with no information given ? 10h: the specified block is not available ? 12h: the specified block is locked and its contents cannot be changed ? 13h: the specified block was not successfully programmed when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the write single block command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy pin is tied to 0 for the duration of the internal write cycle (from the en d of a valid write single block command to the beginning of the M24LR64E-R response). table 46. write single block response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - figure 55. write single block frame ex change between vcd and M24LR64E-R vcd sof write single block request eof M24LR64E-R <-t 1 -> sof write single block response eof write sequence when error M24LR64E-R <------------------- w t ---------------> sof write single block response eof command codes M24LR64E-R 86/141 docid022712 rev 7 figure 56. m24lr64e rf-busy management following write command 0 6 9 6 2 ) : u l w h f r p p d q g ( 2 ) 6 2 ) , u h s o \ 0 / 5 [ ( 2 ) 0 / 5 [ u h s o l h v 5 ) b % x v \ l v u h o h d v h g d i w h u 0 / 5 [ u h v s r q v h 5 ) b % x v \ 6 2 ) : u l w h f r p p d q g ( 2 ) ( 2 ) 0 / 5 [ u h s o l h v z k h q r s w l r q i o d j l v v h w 5 ) b % x v \ l v u h o h d v h g d i w h u 0 / 5 [ u h v s r q v h 5 ) b % x v \ : w : w w 6 2 ) , u h s o \ 0 / 5 [ ( 2 ) 9 & ' v h q g v d i r u e l g g h q : u l w h v h f w r u o r f n s d v v z r u g s u r w h f w h g 5 ) b % x v \ l v u h o h d v h g d i w h u 0 / 5 [ f r p p d q g 6 2 ) : u l w h f r p p d q g ( 2 ) 6 2 ) , u h s o \ 0 / 5 [ ( 2 ) w 5 ) b % x v \ docid022712 rev 7 87/141 M24LR64E-R command codes when configuring in the rf write in progre ss mode, the rf wip/busy pin is tied to 0 during the write & verify sequence, as shown in figure 57 . figure 57. m24lr64e rf-wip management following write command 0 6 9 6 2 ) : u l w h f r p p d q g ( 2 ) 6 2 ) , u h s o \ 0 / 5 [ ( 2 ) 0 / 5 [ u h s o l h v 5 ) b : l s l v u h o h d v h g d i w h u 0 / 5 [ u h v s r q v h 5 ) b : l s 6 2 ) : u l w h f r p p d q g ( 2 ) ( 2 ) 0 / 5 [ u h s o l h v z k h q r s w l r q i o d j l v v h w 5 ) b : l s l v u h o h d v h g d i w h u 0 / 5 [ u h v s r q v h 5 ) b : l s : w : w w 6 2 ) , u h s o \ 0 / 5 [ ( 2 ) 9 & ' v h q g v d i r u e l g g h q : u l w h v h f w r u o r f n s d v v z r u g s u r w h f w h g 5 ) b : l s l v u h o h d v h g d i w h u 0 / 5 [ f r p p d q g 6 2 ) : u l w h f r p p d q g ( 2 ) 6 2 ) , u h s o \ 0 / 5 [ ( 2 ) w 5 ) b : l s command codes M24LR64E-R 88/141 docid022712 rev 7 26.5 read multiple block when receiving the read multiple block co mmand, the M24LR64E-R reads the selected blocks and sends back their value in multiple s of 32 bits in the response. the blocks are numbered from 00h to 1ffh in the request and the value is minus one (?1) in the field. for example, if the ?number of blocks? field cont ains the value 06h, seven blocks are read. the maximum number of blocks is fixed at 32 assumi ng that they are all located in the same sector. if the number of blocks overlaps sectors, the M24LR64E-R returns an error code. the protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. if the protocol_extension_flag is at 0, the m 24lr64e-r answers with an error code. the option_flag is supported. request parameters: ? request flags ? uid (optional) ? first block number ? number of blocks response parameters: ? sector security status if option_flag is set (see table 49 ) ? n blocks of data table 47. read multiple block request format request sof request_ flags read multiple block uid (1) 1. gray color means that the field is optional. first block number number of blocks crc16 request eof -8 bits 23h 64 bits 16 bits 8 bits 16 bits - table 48. read multiple block response format when error_flag is not set response sof response_ flags sector security status (1) 1. gray color means that the field is optional. data crc16 response eof -8 bits 8 bits (2) 2. repeated as needed. 32 bits (2) 16 bits - table 49. sector security status b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved for future use. all at 0. password control bits read / write protection bits 0: current sector not locked 1: current sector locked table 50. read multiple block response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - docid022712 rev 7 89/141 M24LR64E-R command codes response parameter: ? error code as error_flag is set: ? 0fh: error with no information given ? 10h: the specified block is not available ? 15h: the specified block is read-protected when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the read multiple block command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. 26.6 select when receiving the select command: ? if the uid is equal to its own uid, the m2 4lr64e-r enters or stays in the selected state and sends a response. ? if the uid does not match its own uid, the selected M24LR64E-R returns to the ready state and does not send a response. the M24LR64E-R answers an error code only if the uid is equal to its own uid. if not, no response is generated. if an error occurs, the M24LR64E-R remains in its current state. request parameter: ? uid figure 58. read multiple block frame exchange between vcd and M24LR64E-R vcd sof read multiple block request eof M24LR64E-R <-t 1 -> sof read multiple block response eof table 51. select request format request sof request_flags select uid crc16 request eof - 8 bits 25h 64 bits 16 bits - table 52. select block response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - command codes M24LR64E-R 90/141 docid022712 rev 7 response parameter: ? no parameter response parameter: ? error code as error_flag is set: ? 03h: the option is not supported when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the select command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. 26.7 reset to ready on receiving a reset to ready command, the M24LR64E-R returns to the ready state if no error occurs. in the addressed mode, the M24LR64E-R answers an error code only if the uid is equal to its own uid. if not, no response is generated. request parameter: ? uid (optional) table 53. select response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - figure 59. select frame exchange between vcd and M24LR64E-R vcd sof select request eof M24LR64E-R <-t 1 -> sof select response eof table 54. reset to ready request format request sof request_flags reset to ready uid (1) 1. gray color means that the field is optional. crc16 request eof - 8 bits 26h 64 bits 16 bits - docid022712 rev 7 91/141 M24LR64E-R command codes response parameter: ? no parameter response parameter: ? error code as error_flag is set: ? 03h: the option is not supported when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the reset to ready command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. 26.8 write afi on receiving the write afi request, the m24lr 64e-r programs the 8-bit afi value to its memory. the option_flag is supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%), otherwise the M24LR64E-R may not write correctly the afi value into the memory. the w t time is equal to t 1nom + 18 302 s. table 55. reset to ready response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - table 56. reset to ready response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - figure 60. reset to ready frame exchange between vcd and M24LR64E-R vcd sof reset to ready request eof M24LR64E-R <-t 1 -> sof reset to ready response eof command codes M24LR64E-R 92/141 docid022712 rev 7 request parameter: ? request flags ? uid (optional) ? afi response parameter: ? no parameter response parameter: ? error code as error_flag is set ? 12h: the specified block is locked and its contents cannot be changed ? 13h: the specified block was not successfully programmed table 57. write afi request format request sof request_flags write afi uid (1) 1. gray color means that the field is optional. afi crc16 request eof - 8 bits 27h 64 bits 8 bits 16 bits - table 58. write afi response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - table 59. write afi response format when error_flag is set response sof response_ flags error code crc16 response eof - 8 bits 8 bits 16 bits - figure 61. write afi frame exchange between vcd and M24LR64E-R vcd sof write afi request eof M24LR64E-R <-t 1 -> sof write afi response eof write sequence when error M24LR64E-R <------------------ w t --------------> sof write afi response eof docid022712 rev 7 93/141 M24LR64E-R command codes when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the write afi command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy pin is tied to 0 for the duration of the internal write cycle (from th e end of a valid write afi command to the beginning of the M24LR64E-R response). 26.9 lock afi on receiving the lock afi request, the m24l r64e-r locks the afi va lue permanently. the option_flag is supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%), otherwise the M24LR64E-R may not lock correctly the afi value in memory. the w t time is equal to t 1nom + 18 302 s. request parameter: ? request flags ? uid (optional) response parameter: ? no parameter response parameter: ? error code as error_flag is set ? 11h: the specified block is already locked and thus cannot be locked again ? 14h: the specified block was not successfully locked table 60. lock afi request format request sof request_flag slock afi uid (1) 1. gray color means that the field is optional. crc16 request eof - 8 bits 28h 64 bits 16 bits - table 61. lock afi response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - table 62. lock afi response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - command codes M24LR64E-R 94/141 docid022712 rev 7 when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the lock afi command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy pin is tied to 0 for the entire duration of the internal write cycle (f rom the end of valid lock afi command to the beginning of the M24LR64E-R response). figure 62. lock afi frame exchange between vcd and M24LR64E-R vcd sof lock afi request eof M24LR64E-R <-t 1 -> sof lock afi response eof lock sequence when error M24LR64E-R <----------------- w t -----------> sof lock afi response eof docid022712 rev 7 95/141 M24LR64E-R command codes 26.10 write dsfid on receiving the write dsfid request, the m2 4lr64e-r programs the 8-bit dsfid value to its memory. the option_flag is supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%), otherwise the M24LR64E-R may not write correctly the dsfid value in memory. the w t time is equal to t 1nom + 18 302 s. request parameter: ? request flags ? uid (optional) ? dsfid response parameter: ? no parameter response parameter: ? error code as error_flag is set ? 12h: the specified block is locked and its contents cannot be changed ? 13h: the specified block was not successfully programmed table 63. write dsfid request format request sof request_flags w rite dsfid uid (1) 1. gray color means that the field is optional. dsfid crc16 request eof - 8 bits 29h 64 bits 8 bits 16 bits - table 64. write dsfid response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - table 65. write dsfid response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - command codes M24LR64E-R 96/141 docid022712 rev 7 when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the write dsfid command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy pin is tied to 0 for the duration of the internal write cycle (from th e end of a valid write dsfid command to the beginning of the M24LR64E-R response). 26.11 lock dsfid on receiving the lock dsfid request, the M24LR64E-R locks the dsfid value permanently. the option_flag is supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%), otherwise the M24LR64E-R may not lock correctly the dsfid value in memory. the w t time is equal to t 1nom + 18 302 s. request parameter: ? request flags ? uid (optional) figure 63. write dsfid frame exchange between vcd and M24LR64E-R vcd sof write dsfid request eo f M24LR64E-R <-t 1 -> so f write dsfid response eo f write sequence when error M24LR64E-R <---------------- w t ----------> so f write dsfid response eof table 66. lock dsfid request format request sof request_flags lock dsfid uid (1) 1. gray color means that the field is optional. crc16 request eof -8 bits 2ah 64 bits 16 bits - table 67. lock dsfid response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - docid022712 rev 7 97/141 M24LR64E-R command codes response parameter: ? no parameter. response parameter: ? error code as error_flag is set: ? 11h: the specified block is already locked and thus cannot be locked again ? 14h: the specified block was not successfully locked when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the lock dsfid command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy pin is tied to 0 for the duration of the internal write cycle (from th e end of a valid lock dsfid command to the beginning of the M24LR64E-R response). 26.12 get system info when receiving the get system info command, the M24LR64E-R sends back its information data in the response. the option_flag is not supported. the get system info can be issued in both addressed and non addressed modes. the protocol_extension_flag can be set to 0 or 1. table 70 and table 72 show m24lr64e- r response to the get system info command depending on the value of the protocol_extension_flag. table 68. lock dsfid response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - figure 64. lock dsfid frame exchange between vcd and M24LR64E-R vcd sof lock dsfid request eof M24LR64E-R <-t 1 -> sof lock dsfid response eof lock sequence when error M24LR64E-R <---------------- w t -------------> sof lock dsfid response eof command codes M24LR64E-R 98/141 docid022712 rev 7 request parameter: ? request flags ? uid (optional) response parameters: ? information flags set to 0ch. dsfid, afi and ic reference fields are present. ? uid code on 64 bits ? dsfid value ? afi value ? M24LR64E-R ic reference: the 8 bits are significant. response parameters: ? information flags set to 0fh. dsfid, afi, memory size and ic reference fields are present. ? uid code on 64 bits ? dsfid value ? afi value ? memory size. the M24LR64E-R provides 2048 blocks (07ffh) of 4 bytes (03h) ? ic reference: the 8 bits are significant. table 69. get system info request format request sof request_flags get system info uid (1) 1. gray color means that the field is optional. crc16 request eof - 8 bits 2bh 64 bits 16 bits - table 70. get system info response format when protocol_extension_flag = 0 and error_flag is not set response sof response_ flags information flags uid dsfid afi ic ref. crc16 response eof - 00h 0bh 64 bits 8 bits 8 bits 5eh 16 bits - table 71. get system info response format when protocol_extension_flag = 1 and error_flag is not set response sof response _flags information flags uid dsfid afi memory size ic ref crc16 response eof - 00h 0fh 64 bits 8 bits 8 bits 03 07ffh 5eh 16 bits - table 72. get system info response format when error_flag is set response sof response_flags error code crc16 response eof - 01h 8 bits 16 bits - docid022712 rev 7 99/141 M24LR64E-R command codes response parameter: ? error code as error_flag is set: ? 03h: option not supported . when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the get system info command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. 26.13 get multiple bl ock security status when receiving the get multiple block securi ty status command, the M24LR64E-R sends back the sector security status. the blocks are numbered from 00h to 01ffh in the request and the value is minus one (?1) in the field. fo r example, a value of '06' in the ?number of blocks? field requests to return th e security status of seven blocks. the protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. if the protocol_extension_flag is at 0, th e M24LR64E-R answers with an error code. during the M24LR64E-R response, if the inte rnal block address counter reaches 01ffh, it rolls over to 0000h and the sector security stat us bytes for that location are sent back to the reader. request parameter: ? request flags ? uid (optional) ? first block number ? number of blocks figure 65. get system info frame exchange between vcd and M24LR64E-R vcd sof get system info request eof M24LR64E-R <-t 1 -> sof get system info response eof table 73. get multiple block security status request format request sof request _flags get multiple block security status uid (1) 1. gray color means that the field is optional. first block number number of blocks crc16 request eof -8 bits 2ch 64 bits 16 bits 16 bits 16 bits - command codes M24LR64E-R 100/141 docid022712 rev 7 response parameters: ? sector security status (see table 75 ) response parameter: ? error code as error_flag is set: ? 03h: the option is not supported ? 10h: the specified block is not available when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the get multiple block security status command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. table 74. get multiple block security status response format when error_flag is not set response sof response_flags sector security status crc16 response eof - 8 bits 8 bits (1) 1. repeated as needed. 16 bits - table 75. sector security status b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved for future use all at 0 password control bits read / write protection bits 0: current sector not locked 1: current sector locked table 76. get multiple block security status response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - figure 66. get multiple block security status frame exchange between vcd and M24LR64E-R vcd sof get multiple block security status eof M24LR64E-R <-t 1 -> sof get multiple block security status eof docid022712 rev 7 101/141 M24LR64E-R command codes 26.14 write-sector password on receiving the write-sector password command, the M24LR64E-R uses the data contained in the request to write the password and reports whether the operation was successful in the response. the option_flag is supported. during the rf write cycle time, w t , there must be no modulation at all (neither 100% nor 10%), otherwise the M24LR64E-R may not correctly program the data into the memory. the w t time is equal to t 1nom + 18 302 s. after a successful write, the new value of the selected password is automatically activated. it is not required to present the new password value until M24LR64E-R power-down. request parameter: ? request flags ? uid (optional) ? password number (01h = pswd1, 02h = pswd2, 03h = pswd3, other = error) ? data response parameter: ? no parameter. response parameter: ? error code as error_flag is set: ? 10h: the password number is incorrect ? 12h: the session was not opened before the password update ? 13h: the specified block was not successfully programmed ? 0fh: the presented password is incorrect table 77. write-sector password request format request sof request _flags write-sector password ic mfg code uid (1) 1. gray color means that the field is optional. password number data crc16 request eof -8 bits b1h02h 64 bits 8 bits 32 bits 16 bits - table 78. write-sector password response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - table 79. write-sector password response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - command codes M24LR64E-R 102/141 docid022712 rev 7 when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the write-sector password command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy pin is tied to 0 for the duration of the internal write cycle (from the end of a valid write sector password command to the beginning of the M24LR64E-R response). 26.15 lock-sector on receiving the lock-sector command, the M24LR64E-R sets the access rights and permanently locks the selected sect or. the option_flag is supported. a sector is selected by giving the address of one of its blocks in the lock-sector request (sector number field). for example, addresses 0 to 31 are used to select sector 0 and addresses 32 to 63 are used to select sector 1. care must be taken when issuing the lock- sector command as all the blocks belonging to the same sector are automatically locked by a single command. the protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. if the protocol_extension_flag is at 0, th e M24LR64E-R answers with an error code. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%), otherwise the M24LR64E-R may not correctly lock the memory block. the w t time is equal to t 1nom + 18 302 s. figure 67. write-sector password frame exchange between vcd and M24LR64E-R vcd sof write- sector password request eof M24LR64E-R <-t 1 -> sof write-sector password response eof write sequence when error M24LR64E-R <---------------- w t -------------> sof write- sector password response eof table 80. lock-sector request format request sof request _flags lock- sector ic mfg code uid (1) 1. gray color means that the field is optional. sector number sector security status crc16 request eof - 8 bits b2h 02h 64 bits 16 bits 8 bits 16 bits - docid022712 rev 7 103/141 M24LR64E-R command codes request parameters: ? request flags ? (optional) uid ? sector number ? sector security status (refer to table 81 ) response parameter: ? no parameter response parameter: ? error code as error_flag is set: ? 10h: the specified block is not available ? 11h: the specified block is already locked and thus cannot be locked again ? 14h: the specified block was not successfully locked table 81. sector security status b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 0 password control bits read / write protection bits 1 table 82. lock-sector response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - table 83. lock-sector response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - figure 68. lock-sector frame exchange between vcd and M24LR64E-R vcd sof lock-sector request eof M24LR64E-R <-t 1 -> sof lock-sector response eof lock sequence when error M24LR64E-R <--------------- w t -----------> sof lock-sector response eof command codes M24LR64E-R 104/141 docid022712 rev 7 when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the lock-sector command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy pin is tied to 0 for the duration of the internal write cycle (from the end of a valid lock sector command to the beginning of the M24LR64E-R response). 26.16 present-sector password on receiving the present-sector password command, the M24LR64E-R compares the requested password with the data contained in the request and reports whether the operation has been successful in the re sponse. the option_flag is supported. during the comparison cycle equal to w t , there should be no modulation (neither 100% nor 10%), otherwise the M24LR64E-R password value may not be correctly compared. the w t time is equal to t 1nom + 18 302 s. after a successful command, the access to all the memory blocks linked to the password is changed as described in section 4.1: M24LR64E-R block security in rf mode . request parameter: ? request flags ? uid (optional) ? password number (0x01 = pswd1, 0x02 = pswd2, 0x03 = pswd3, other = error) ? password response parameter: ? no parameter. the response is sent back after the write cycle. table 84. present-sector password request format request sof request _flags present- sector password ic mfg code uid (1) 1. gray color means that the field is optional. password number password crc16 request eof -8 bitsb3h02h 64 bits 8 bits 32 bits 16 bits - table 85. present-sector password response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - table 86. present-sector password response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - docid022712 rev 7 105/141 M24LR64E-R command codes response parameter: ? error code as error_flag is set: ? 10h: the password number is incorrect ? 0fh: the present password is incorrect when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the present sector password command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy remains in high-z state. 26.17 fast read single block on receiving the fast read single block command, the M24LR64E-R reads the requested block and sends back its 32-bit value in the response. the option_flag is supported. the data rate of the response is multiplied by 2. the protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. if the protocol_extension_flag is at 0, the M24LR64E-R answers with an error code. the subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error code. figure 69. present-sector password frame exchange between vcd and M24LR64E-R vcd sof present- sector password response or error 0f (bad password) eof M24LR64E-R <-t 1 -> sof present- sector password response eof sequence when error M24LR64E-R <---------------- w t ------------> sof present- sector password response eof table 87. fast read single block request format request sof request_flags fast read single block ic mfg code uid (1) 1. gray color means that the field is optional. block number crc16 request eof -8 bits c0h02h 64 bits 16 bits 16 bits - command codes M24LR64E-R 106/141 docid022712 rev 7 request parameters: ? request flags ? uid (optional) ? block number response parameters: ? sector security status if option_flag is set (see table 89 ) ? four bytes of block data response parameter: ? error code as error_flag is set: ? 10h: the specified block is not available ? 15h: the specified block is read-protected when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the fast read single block command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. table 88. fast read single block response format when error_flag is not set response sof response_flags sector security status (1) 1. gray color means that the field is optional. data crc16 response eof -8 bits 8 bits 32 bits 16 bits - table 89. sector security status b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved for future use all at 0 password control bits read / write protection bits 0: current sector not locked 1: current sector locked table 90. fast read single block resp onse format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - figure 70. fast read single block fram e exchange between vcd and M24LR64E-R vcd sof fast read single block request eof M24LR64E-R <-t 1 -> sof fast read single block response eof docid022712 rev 7 107/141 M24LR64E-R command codes 26.18 fast inventory initiated before receiving the fast inventory initiated command, the M24LR64E-R must have received an initiate or a fast initiate command in order to set the initiate_ flag. if not, the M24LR64E-R does not answer the fast inventory initiated command. the subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error code. on receiving the fast invent ory initiated request, the m24l r64e-r runs the anticollision sequence. the inventory_flag must be set to 1. the meaning of flags 5 to 8 is shown in table 29 . the data rate of the response is multiplied by 2. the request contains: ? the flags, ? the inventory command code, ? the afi if the afi flag is set, ? the mask length, ? the mask value, ? the crc. the M24LR64E-R does not generate any answer in case of error. the response contains: ? the flags, ? the unique id. during an inventory process, if the vcd does not receive an rf M24LR64E-R response, it waits for a time t 3 before sending an eof to switch to the next slot. t 3 starts from the rising edge of the request eof sent by the vcd. ? if the vcd sends a 100% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t sof ? if the vcd sends a 10% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t nrt where: ? t sof is the time required by the m24lr 64e-r to transmit an sof to the vcd ? t nrt is the nominal response time of the M24LR64E-R table 91. fast inventory initiated request format request sof request _flags fast inventory initiated ic mfg code optional afi mask length mask value crc16 request eof - 8 bits c1h 02h 8 bits 8 bits 0 - 64 bits 16 bits - table 92. fast inventory initiated response format response sof response_flags dsfid uid crc16 response eof - 8 bits 8 bits 64 bits 16 bits - command codes M24LR64E-R 108/141 docid022712 rev 7 t nrt and t sof are dependent on the M24LR64E-R-to-vcd data rate and subcarrier modulation mode. when configured in the rf busy mode, the rf wip/busy pin is driven to 0 from the sof starting the inventory command to the end of the M24LR64E-R response. if the m24lr64e- r does not receive the corresponding slot marker, the rf wip/busy pin remains at 0 until the next rf power-off. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. 26.19 fast initiate on receiving the fast initiate command, the M24LR64E-R sets the internal initiate_flag and sends back a response only if it is in the ready state. the command has to be issued in the non addressed mode only (select_flag is reset to 0 and address_flag is reset to 0). if an error occurs, the M24LR64E-R does not generate any answer. the initiate_flag is reset after a power-off of the M24LR64E-R. the data rate of the response is multiplied by 2. the subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error code. the request contains: ? no data the response contains: ? the flags, ? the unique id. table 93. fast initiate request format request sof request_flags fast initiate ic mfg code crc16 request eof - 8 bits c2h 02h 16 bits - table 94. fast initiate response format response sof response_flags dsfid uid crc16 response eof - 8 bits 8 bits 64 bits 16 bits - figure 71. fast initiate frame exchange between vcd and M24LR64E-R vcd sof fast initiate request eof M24LR64E-R <-t 1 -> sof fast initiate response eof docid022712 rev 7 109/141 M24LR64E-R command codes when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the fast initiate command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy pin remains in high-z state. 26.20 fast read multiple block on receiving the fast read multiple block command, the M24LR64E-R reads the selected blocks and sends back their value in multiple s of 32 bits in the response. the blocks are numbered from 00h to 1ffh in the request and the value is minus one (?1) in the field. for example, if the ?number of blocks? field cont ains the value 06h, seven blocks are read. the maximum number of blocks is fixed to 32 assumi ng that they are all located in the same sector. if the number of blocks overlaps sectors, the M24LR64E-R returns an error code. the protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. if the protocol_extension_flag is at 0, th e M24LR64E-R answers with an error code. the option_flag is supported. the data ra te of the response is multiplied by 2. the subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error code. request parameters: ? request flag ? uid (optional) ? first block number ? number of blocks response parameters: ? sector security status if option_flag is set (see table 97 ) ? n block of data table 95. fast read multiple block request format request sof request_ flags fast read multiple block ic mfg code uid (1) 1. gray color means that the field is optional. first block number number of blocks crc16 request eof -8 bits c3h02h 64 bits 16 bits 8 bits 16 bits - table 96. fast read multiple block response format when error_flag is not set response sof response_flags sector security status (1) 1. gray color means that the field is optional. data crc16 response eof -8 bits 8 bits (2) 2. repeated as needed. 32 bits (2) 16 bits - command codes M24LR64E-R 110/141 docid022712 rev 7 response parameter: ? error code as error_flag is set: ? 03h: the option is not supported ? 10h: block address not available ? 15h: block read-protected when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the fast read multiple block command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. 26.21 inventory initiated before receiving the inventory initiated command, the M24LR64E-R must have received an initiate or a fast initiate co mmand in order to set the initia te_ flag. if not, the M24LR64E-R does not answer the inventory initiated command. on receiving the inventory in itiated reques t, the M24LR64E-R ru ns the anticollision sequence. the inventory_flag must be set to 1. the meaning of flags 5 to 8 is given in table 29 . table 97. sector security st atus if option_flag is set b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved for future use all at 0 password control bits read / write protection bits 0: current sector not locked 1: current sector locked table 98. fast read multiple block response format when error_flag is set response sof response_flags e rror code crc16 response eof - 8 bits 8 bits 16 bits - figure 72. fast read multiple block frame exchange between vcd and M24LR64E-R vcd sof fast read multiple block request eof M24LR64E-R <-t 1 -> sof fast read multiple block response eof docid022712 rev 7 111/141 M24LR64E-R command codes the request contains: ? the flags, ? the inventory command code, ? the afi if the afi flag is set, ? the mask length, ? the mask value, ? the crc. the M24LR64E-R does not generate any answer in case of error. the response contains: ? the flags, ? the unique id. during an inventory process, if the vcd does not receive an rf M24LR64E-R response, it waits for a time t 3 before sending an eof to switch to the next slot. t 3 starts from the rising edge of the request eof sent by the vcd. ? if the vcd sends a 100% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t sof ? if the vcd sends a 10% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t nrt where: ? t sof is the time required by the m24lr 64e-r to transmit an sof to the vcd ? t nrt is the nominal response time of the M24LR64E-R t nrt and t sof are dependent on the M24LR64E-R-to-vcd data rate and subcarrier modulation mode. when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof starting the inventory command to the end of the M24LR64E-R response. if the m24lr64e- r does not receive the corresponding slot marker, the rf wip/busy pin remains at 0 until the next rf power-off. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. table 99. inventory initiated request format request sof request _flags inventory initiated ic mfg code optional afi mask length mask value crc16 request eof - 8 bits d1h 02h 8 bits 8 bits 0 - 64 bits 16 bits - table 100. inventory initiated response format response sof response_flags dsfid uid crc16 response eof - 8 bits 8 bits 64 bits 16 bits - command codes M24LR64E-R 112/141 docid022712 rev 7 26.22 initiate on receiving the initiate co mmand, the M24LR64E-R sets the internal initiate_flag and sends back a response only if it is in the ready state. the command has to be issued in the non addressed mode only (select_flag is reset to 0 and address_flag is reset to 0). if an error occurs, the M24LR64E-R does not generate any answer. the initiate_flag is reset after a power-off of the M24LR64E-R. the request contains: ? no data the response contains: ? the flags, ? the unique id. when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the initiate command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. 26.23 readcfg on receiving the readcfg command, the m24l r64e-r reads the configuration byte and sends back its 8-bit va lue in the response. table 101. initiate request format request sof request_flags initiate ic mfg code crc16 request eof - 8 bits d2h 02h 16 bits - table 102. initiate response format response sof response_flags dsfid uid crc16 response eof - 8 bits 8 bits 64 bits 16 bits - figure 73. initiate frame exchange between vcd and M24LR64E-R vcd sof initiate request eof M24LR64E-R <-t 1 -> sof initiate response eof docid022712 rev 7 113/141 M24LR64E-R command codes the protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. if the protocol_extension_flag is at 1, the m 24lr64e-r answers with an error code. the option_flag is not supported. the inventory_flag must be set to 0. request parameters: ? uid (optional) response parameters: ? one byte of data: configuration byte response parameter: ? error code as error_flag is set ? 03h: the option is not supported ? 0fh: error with no information given figure 74. readcfg frame exchange between vcd and M24LR64E-R when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the readcfg command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. table 103. readcfg request format request sof request_flags readcfg ic mfg code uid (1) 1. gray color means that the field is optional. crc16 request eof - 8 bits a0h 02h 64 bits 16 bits - table 104. readcfg response format when error_flag is not set response sof response_flags data crc16 response eof - 8 bits 8 bits 16 bits - table 105. readcfg response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - vcd sof readcfg request eof M24LR64E-R <-t 1 -> sof readcfg response eof command codes M24LR64E-R 114/141 docid022712 rev 7 26.24 writeehcfg on receiving the writeehcfg command, the M24LR64E-R writes the data contained in the request to the configuration byte and reports whether the write operation was successful in the response. the protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. if the protocol_extension_fla g is at 1, the M24LR64E-R answers with an error code. the option_flag is supported, the inventory_flag is not supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%), otherwise the M24LR64E-R may not program correc tly the data into the configuration byte. the w t time is equal to t 1nom + 18 302 s. request parameters: ? request flags ? uid (optional) ? data: during writeehcfg command, bit 3 of the data is ignored (see table 14 ). response parameter: ? no parameter. the response is sent back after the writing cycle. response parameter: ? error code as error_flag is set: ? 13h: the specified block was not successfully programmed table 106. writeehcfg request format request sof request_flags writeehcfg ic mfg code uid (1) 1. gray color means that the field is optional. data crc16 request eof -8 bits a1h 02h 64 bits 8 bits 16 bits - table 107. writeehcfg response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - table 108. writeehcfg response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - docid022712 rev 7 115/141 M24LR64E-R command codes when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the writeehcfg command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy pin is tied to 0 for the entire duration of the internal write cycle (f rom the end of a valid writeehcfg command to the beginning of the M24LR64E-R response). 26.25 writedocfg on receiving the writedocfg command, the M24LR64E-R writes the data contained in the request to the configuration byte and reports whether the write operation was successful in the response. the protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. if the protocol_extensi on_flag is at 1, the M24LR64E-R answers with an error code. the option_flag is supported, the inventory_flag is not supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%), otherwise the M24LR64E-R may not program correc tly the data into the configuration byte. the w t time is equal to t 1nom + 18 302 s. request parameters: ? request flag ? uid (optional) ? data: during a writedocfg command, bits 2 to 0 of the data are ignored (see table 14 ). figure 75. writeehcfg frame exchange between vcd and M24LR64E-R vcd sof writeehcfg request eof M24LR64E-R <-t 1 -> sof writeehcfg response eof writeehcfg sequence when error M24LR64E-R <------------------- w t ---------------> sof writeehcfg response eof table 109. writedocfg request format request sof request_ flags writedocfg ic mfg code uid (1) 1. gray color means that the field is optional. data crc16 request eof - 8 bits a4h 02h 64 bits 8 bits 16 bits - command codes M24LR64E-R 116/141 docid022712 rev 7 response parameter: ? no parameter. the response is sent back after the writing cycle. response parameter: ? error code as error_flag is set: ? 13h: the specified block was not successfully programmed when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the writeehcfg command to the end of the M24LR64E-R response. when configured in the rf write in progress mode, the rf wip/busy pin is tied to 0 for the entire duration of the internal write cycle (f rom the end of a valid writedocfg command to the beginning of the M24LR64E-R response). 26.26 setrstehen on receiving the setrstehen command, the M24LR64E-R sets or resets the eh_enable bit in the volatile control register. the protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. if the pr otocol_extension_flag is at 1, the M24LR64E-R answers with an error code. the option_flag and the inventory_flag are not supported. table 110. writedocfg response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - table 111. writedocfg response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - figure 76. writedocfg frame exchange between vcd and M24LR64E-R vcd sof writedocfg request eof M24LR64E-R <-t 1 -> sof writedocfg response eof writedocfg sequence when error M24LR64E-R <----------------- w t --------------> sof writedocfg response eof docid022712 rev 7 117/141 M24LR64E-R command codes request parameters: ? request flags ? uid (optional) ? data: during a setrstehen command, bits 7 to 1 are ignored. bit 0 is the eh_enable bit. response parameter: ? no parameter. the response is sent back after t 1 . response parameter: ? error code as error_flag is set: ? 03h: the option is not supported when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the setrstehen command to the end of the M24LR64E-R response. table 112. setrstehen request format request sof request_flags setrstehen ic mfg code uid (1) 1. gray color means that the field is optional. data crc16 request eof -8 bits a2h 02h 64 bits 8 bits 16 bits - table 113. setrstehen response format when error_flag is not set response sof response_flags crc16 response eof - 8 bits 16 bits - table 114. setrstehen response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - figure 77. setrstehen frame exchange between vcd and M24LR64E-R vcd sof setrstehen request eof M24LR64E-R <-t 1 -> sof setrstehen response eof writeehcfg sequence when no error M24LR64E-R <-t 1 -> sof setrstehen response eof writeehcfg sequence when error command codes M24LR64E-R 118/141 docid022712 rev 7 when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. 26.27 checkehen on receiving the checkehen command, the M24LR64E-R reads the control register and sends back its 8-bit va lue in the response. the protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. if the protocol_extension_flag is at 1, the m 24lr64e-r answers with an error code. the option_flag is not supported. the inventory_flag must be set to 0. request parameters: ? uid (optional) response parameters: ? one byte of data: volatile control register (see table 15 ) response parameter: ? error code as error_flag is set ? 03h: the option is not supported table 115. checkehen request format request sof request_flags checkehen ic mfg code uid (1) 1. gray color means that the field is optional. crc16 request eof - 8 bits a3h 02h 64 bits 16 bits - table 116. checkehen response format when error_flag is not set response sof response_flags data crc16 response eof - 8 bits 8 bits 16 bits - table 117. checkehen response format when error_flag is set response sof response_flags error code crc16 response eof - 8 bits 8 bits 16 bits - docid022712 rev 7 119/141 M24LR64E-R command codes when configured in the rf busy mode, the rf wip/busy pin is tied to 0 from the sof that starts the checkehen command to the end of the M24LR64E-R response. when configured in the rf wr ite in progress mode, the rf wip/busy pin remains in high-z state. figure 78. checkehen frame exchange between vcd and M24LR64E-R vcd sof checkehen request eof M24LR64E-R <-t 1 -> sof checkehen response eof maximum rating M24LR64E-R 120/141 docid022712 rev 7 27 maximum rating stressing the device ab ove the rating listed in table 118 may cause permanent damage to the device. these are stress ratings only and operation of the device, at these or any other conditions above those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect the device reliability. refer also to t he stmicroelectronics sure program and other relevant quality documents. table 118. absolute maximum ratings symbol parameter min. max. unit t a ambient operating temperature ?40 85 c t stg , h stg , t stg storage conditions sawn wafer on uv tape 15 25 c -6 (1) 1. counted from st shipment date. months kept in its original packing form t stg storage temperature ufdfpn8 (mlp8), so8, tssop8 ?65 150 c t lead lead temperature during soldering ufdfpn8 (mlp8), so8, tssop8 see note (2) 2. compliant with jedec std j-std-020c (for sm all body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. c v io i 2 c input or output range ?0.50 6.5 v v cc i 2 c supply voltage ?0.50 6.5 v i ol_max dc output current on pin sda or rf wip/busy (when equal to 0) -5ma i cc (3) 3. based on characterization, not tested in production. rf supply current ac0 - ac1 - 50 ma v max_1 (3) rf input voltage amplitude peak to peak between ac0 and ac1, gnd pad left floating vac0-vac1 - 27 v v max_2 (3) ac voltage between ac0 and gnd, or ac1 and gnd vac0-gnd, or vac1-gnd -1 11 v v esd electrostatic discharge voltage (human body model) (4) 4. aec-q100-002 (compliant with jedec std jesd22-a114a, c1 = 100 pf, r1 = 1500 , r2 = 500 ) ac0, ac1 - 1000 v other pads - 3500 electrostatic discharge voltage (machine model) - 400 electrostatic discharge voltage on antenna (5) 5. compliant with iec 61000-4-3 method. (m24lr xxe packaged in s08n is mounted on st?s reference antenna ant1- m24lrxxe) ac0, ac1 - 4000 docid022712 rev 7 121/141 M24LR64E-R i 2 c dc and ac parameters 28 i 2 c dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device in i 2 c mode. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the op erating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 79. ac test measurement i/o waveform table 119. i 2 c operating conditions symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 120. ac test measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf t r, t f input rise and fall times - 50 ns v hi-lo input levels 0.2v cc to 0.8v cc v v ref(t) input and output timing reference levels 0.3v cc to 0.7v cc v table 121. input parameters symbol parameter min. max. unit c in input capacitance (sda) - 8 pf c in input capacitance (other pins) - 6 pf t ns (1) 1. characterized only. pulse width ignored (input filter on scl and sda) - 80 ns $ , % x? s x? s x s x? s /v?? v k??? d]u]vp z ( ? v > o? /v?? > o? i 2 c dc and ac parameters M24LR64E-R 122/141 docid022712 rev 7 table 122. i 2 c dc characteristics symbol parameter test condition min. max. unit i li input leakage current (scl, sda) v in = v ss or v cc device in standby mode - 2a i lo_vout vout output leakage current external voltage applied on vout: v ss or v cc - 5a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) (1) 1. scl, sda connected to ground or v cc. sda connected to v cc through a pull-up resistor. v cc = 1.8 v, f c = 100 khz (rise/fall time < 50 ns) -50 a v cc = 1.8 v, f c = 400 khz (rise/fall time < 50 ns) - 100 v cc = 2.5 v, f c = 400 khz (rise/fall time < 50 ns) - 200 v cc = 5.5 v, f c = 400 khz (rise/fall time < 50 ns) - 400 i cc0 supply current (write) (1) v cc = 1.8 - 5.5 v - 220 a i cc1 standby supply current v in = v ss or v cc v cc = 1.8 v -30 a v in = v ss or v cc v cc = 2.5 v -30 v in = v ss or v cc v cc = 5.5 v - 100 v il input low voltage (sda, scl) v cc = 1.8 v ?0.45 0.25v cc v v cc = 2.5 v ?0.45 0.25v cc v cc = 5.5 v ?0.45 0.3v cc v ih input high voltage (sda, scl) v cc = 1.8 v 0.75v cc v cc +1 v v cc = 2.5 v 0.75v cc v cc +1 v cc = 5.5 v 0.7v cc v cc +1 v ol output low voltage i ol = 2.1 ma, v cc = 1.8 v or i ol = 3 ma, v cc = 5.5 v -0.4v docid022712 rev 7 123/141 M24LR64E-R i 2 c dc and ac parameters table 123. i 2 c ac characteristics test conditions specified in table 119 symbol alt. parameter min. max. unit f c f scl clock frequency 25 400 khz t chcl t high clock pulse width high 0.6 20000 (1) 1. t chcl timeout. s t clch t low clock pulse width low 1.3 20000 (2) 2. t clch timeout. s t start_out - i2c timeout on start condition 40 - ms t xh1xh2 (3) 3. values recommended by the i2c-bus fast-mode specification. t r input signal rise time 20 300 ns t xl1xl2 (3) t f input signal fall time 20 300 ns t dl1dl2 t f sda (out) fall time 20 100 ns t dxcx t su:dat data in set up time 100 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (4) 4. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. t dh data out hold time 100 - ns t clqv (5) 5. t clqv is the time (from the falling edge of scl) required by the sda bus line to reach 0.8v cc in a compatible way with the i 2 c specification (which specifies t su:dat (min) = 100 ns), assuming that the r bus c bus time constant is less than 500 ns (as specified in figure 3 ). t aa clock low to next data valid (access time) 100 900 ns t chdx (6) 6. for a restart condition, or following a write cycle. t su:sta start condition set up time 600 - ns t dlcl t hd:sta start condition hold time 0.6 35000 (7) 7. t dlcl timeout. s t chdh t su:sto stop condition set up time 600 - ns t dhdl t buf time between stop condition and next start condition 1300 - ns t w - i2c write time - 5 ms i 2 c dc and ac parameters M24LR64E-R 124/141 docid022712 rev 7 figure 80. i 2 c ac waveforms 3 # , 3 $ ! ) n 3 # , 3 $ ! / u t 3 # , 3 $ ! ) n t # ( # , t $ , # , t # ( $ 8 3 t a r t c o n d i t i o n t # , # ( t $ 8 # 8 t # , $ 8 3 $ ! ) n p u t 3 $ ! # h a n g e t # ( $ ( t $ ( $ , 3 t o p c o n d i t i o n $ a t a v a l i d t # , 1 6 t # , 1 8 t # ( $ ( 3 t o p c o n d i t i o n t # ( $ 8 3 t a r t c o n d i t i o n 7 r i t e c y c l e t 7 ! ) e 3 t a r t c o n d i t i o n t # ( # , t 8 ( 8 ( t 8 ( 8 ( t 8 , 8 , t 8 , 8 , $ a t a v a l i d t $ , $ , docid022712 rev 7 125/141 M24LR64E-R rf electrical parameters 29 rf electrical parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device in rf mode. the parameters in the dc and ac characterist ics tables that follow are derived from tests performed under the measurement conditi ons summarized in the relevant tables. designers should check that the operating cond itions in their circuit match the measurement conditions when relying on the quoted parameters. table 124. rf characteristics (1) (2) symbol parameter condition min typ max unit f cc external rf signal frequency 13.553 13.56 13.567 mhz h_iso operating field according to iso t a = -40 c to 85 c 150 - 5000 ma/ m mi carrier 10% carrier modulation index (3) mi=(a-b)/(a+b) 150 ma/m > h_iso > 1000 ma/m 15 - 30 % h_iso > 1000 ma/m 10 - 30 t rfr ,t rff 10% rise and fall time - 0.5 - 3.0 s t rfsbl 10% minimum pulse width for bit - 7.1 - 9.44 s mi carrier 100% carrier modulation index mi=(a-b)/(a+b) (4) 95 - 100 % t rfr ,t rff 100% rise and fall time - 0.5 - 3.5 s t rfsbl 100% minimum pulse width for bit - 7 - 9.44 s t min cd minimum time from carrier generation to first data from h-field min - - 1 ms f sh subcarrier frequency high f cc /32 - 423.75 - khz f sl subcarrier frequency low f cc /28 - 484.28 - khz t 1 time for M24LR64E-R response 4224/f s 318.6 320.9 323.3 s t 2 time between commands 4224/f s 309 311.5 314 s w t rf write time (including internal verify) - - 5.75 - ms i cc_rf operating current (read) (5) vac0-vac1 (4 v peak to peak) - 20 - a c tun internal tuning capacitor in so8 (6) f = 13.56 mhz 24.8 27.5 30.2 pf v back backscattered level as defined by iso test iso10373-7 10 - - mv v max_1 (3) rf input voltage amplitude between ac0 and ac1, gnd pad left floating, vac0-vac1 peak to peak (7) ---20v v max_2 (3) ac voltage between ac0 and gnd or between ac1 and gnd --1-8.5v rf electrical pa rameters M24LR64E-R 126/141 docid022712 rev 7 figure 81 shows an ask modulated signal from the vcd to the M24LR64E-R. the test conditions for the ac/dc parameters are: ? close coupling condition with tester antenna (1 mm) ? M24LR64E-R performance measured at the tag antenna ? M24LR64E-R synchronous timing, transmit and receive v min_1 (3) rf input voltage amplitude between ac0 and ac1, gnd pad left floating, vac0-vac1 peak to peak (7) inventory and read operations - 4 4.5 v write operations - 4.5 5 v v min_2 (3) ac voltage between ac0 and gnd or between ac1 and gnd inventory and read operations - 1.8 2 v write operations - 2 2.2 v t rf_off rf off time chip reset 2 - - ms 1. t a = ?40 to 85 c. characterized only. 2. all timing characterizations were performed on a reference antenna with the following characteristics: external size: 75 mm x 48 mm number of turns: 5 width of conductor: 0.5 mm space between two conductors: 0.3 mm value of the tuning capacitor in so8: 27.5 pf (M24LR64E-R) value of the coil: 5 h tuning frequency: 13.56 mhz. 3. 15% (or more) carrier modulation index offers a bett er signal/noise ratio and th erefore a wider operating range with a better noise immunity. 4. temperature range 0 c to 90 c. 5. characterized on bench. 6. characterized only, at room temperature only, measured at vac0-vac1 = 1 v peak to peak. 7. characterized only, at room temperature only. table 124. rf characteristics (1) (2) (continued) symbol parameter condition min typ max unit table 125. operating conditions symbol parameter min. max. unit t a ambient operating temperature ?40 85 c docid022712 rev 7 127/141 M24LR64E-R rf electrical parameters figure 81. ask modulated signal table 126 below summarizes respectively the minimum ac0-ac1 input power level p ac0- ac1_min required for the energy harvesting mode, the corresponding maximum current consumption i sink_max and variation of the analog voltage vout for the various energy harvesting fan-out configurations defined by bits b0 and b1 of the configuration byte. table 126. energy harvesting (1) (2) 1. characterized only. 2. valid from -40 c to +85 c. range h min (3) 3. h min characterized according to iso10373-7 test method. p min (4) 4. p min calculated from dc measurements. we recommend to choose the energy harvesting range in respect with the maximum current requested by the application to avoid any disabling of energy harvesting mode (for example, choos e range 01 for a max consumption of 2ma). vout@i=0 vout@i sink_max i sink_max @p min 00 3.5 a/m 100 mw 2.7 v min 4.5 v max 1.7 v 6 ma 01 2.4 a/m 60 mw 2.7 v min 4.5 v max 1.9 v 3 ma 10 1.6 a/m 30 mw 2.7 v min 4.5 v max 2.1 v 1 ma 11 1.0 a/m 16 mw 2.7 v min 4.5 v max 2.3 v 300 a - 3 6 $ % w 5 ) ) w 5 ) 5 w 5 ) 6 % / w 0 , 1 & ' i & & rf electrical pa rameters M24LR64E-R 128/141 docid022712 rev 7 figure 82. energy harvesting: v out min vs. i sink figure 83. energy harvesting: working domain range 11 - 3 6 7 p v u 7 7 7 7 7 n " n " n " n " * t j o l 0 6 9 ) d q r x w $ p $ p $ p $ p $ $ p $ p ) l h o g + u p v $ p $ p $ p : r u n l q j g r p d l q z k h q 5 d q j h l v v h o h f w h g docid022712 rev 7 129/141 M24LR64E-R rf electrical parameters figure 84. energy harvesting: working domain range 10 figure 85. energy harvesting: working domain range 01 0 6 9 ) d q r x w $ p $ p $ p $ p $ $ p $ p ) l h o g + u p v $ p $ p $ p : r u n l q j g r p d l q z k h q 5 d q j h l v v h o h f w h g 0 6 9 ) d q r x w $ p $ p $ p $ p $ $ p $ p ) l h o g + u p v $ p $ p $ p : r u n l q j g r p d l q z k h q 5 d q j h l v v h o h f w h g rf electrical pa rameters M24LR64E-R 130/141 docid022712 rev 7 figure 86. energy harvesting: working domain range 00 0 6 9 ) d q r x w $ p $ p $ p $ p $ $ p $ p ) l h o g + u p v $ p $ p $ p : r u n l q j g r p d l q z k h q 5 d q j h l v v h o h f w h g docid022712 rev 7 131/141 M24LR64E-R package mechanical data 30 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 87. so8n ? 8-lead plas tic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 127. so8n ? 8-lead pl astic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a - - 1.75 - - 0.0689 a1 - 0.10 0.25 - 0.0039 0.0098 a2 - 1.25 - 0.0492 - b - 0.28 0.48 - 0.0110 0.0189 c - 0.17 0.23 - 0.0067 0.0091 ccc - - 0.10 - - 0.0039 d 4.90 4.80 5.00 0.1929 0.1890 0.1969 e 6.00 5.80 6.20 0.2362 0.2283 0.2441 e1 3.90 3.80 4.00 0.1535 0.1496 0.1575 e 1.27 - - 0.0500 - - h - 0.25 0.50 - - - k-08-08 l - 0.40 1.27 - 0.0157 0.0500 l1 1.04 - - 0.0410 - - 6 2 $ ( f f f e h $ ' f ( k [ ? $ n p p / / $ * $ 8 * ( 3 / $ 1 ( package mechanical data M24LR64E-R 132/141 docid022712 rev 7 figure 88. ufdfpn8 (mlp8) ? 8-lead ultra th in fine pitch dual flat package no lead 2 3mm, package outline 1. drawing is not to scale. 2. the central pad (e2 d2 area in the above illustration) is internally pulled to v ss . it must not be connected to any other voltage or signal line on the pc b, for example during the soldering process. 3. the circle in the top view of the package indicates the position of pin 1. table 128. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 0.550 0.450 0.600 0.0217 0.0177 0.0236 a1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 d 2.000 1.900 2.100 0.0787 0.0748 0.0827 d2 (rev mc) - 1.200 1.600 - 0.0472 0.0630 e 3.000 2.900 3.100 0.1181 0.1142 0.1220 e2 (rev mc) - 1.200 1.600 - 0.0472 0.0630 e 0.500 - - 0.0197 - - k - 0.300 - - 0.0118 - l - 0.300 0.500 - 0.0118 0.0197 l1 - - 0.150 - - 0.0059 l3 - 0.300 - - 0.0118 - eee (2) 2. applied for exposed die paddle and terminal s. exclude embedding part of exposed die paddle from measuring. - 0.080 - - 0.0031 - - 3 6 $ % ! ! e e e , e b $ , % , 0 i n + - # docid022712 rev 7 133/141 M24LR64E-R package mechanical data figure 89. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 129. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a - - 1.2 - - 0.0472 a1 - 0.05 0.15 - 0.002 0.0059 a2 1 0.8 1.05 0.0394 0.0315 0.0413 b - 0.19 0.3 - 0.0075 0.0118 c - 0.09 0.2 - 0.0035 0.0079 cp - - 0.1 - - 0.0039 d 3 2.9 3.1 0.1181 0.1142 0.122 e 0.65 - - 0.0256 - - e 6.4 6.2 6.6 0.252 0.2441 0.2598 e1 4.4 4.3 4.5 0.1732 0.1693 0.1772 l 0.6 0.45 0.75 0.0236 0.0177 0.0295 l1 1 - - 0.0394 - - a - 0 8 0 8 n8 - - 8 - - 7 6 6 2 3 $ 0 & 3 f / ( ( ' $ $ d h e $ / part numbering M24LR64E-R 134/141 docid022712 rev 7 31 part numbering note: parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st char ge. in no event, st wi ll be liable for any customer usage of these engineering samples in production. st quality has to be contacted prior to any decision to use these engineering samples to run qualification activity. table 130. ordering informati on scheme for packaged devices example: M24LR64E-R mn 6 t /2 device type m24lr = dynamic nfc/rfid tag ic 64 = memory size in kbit e = support for energy harvesting operating voltage r = v cc = 1.8 to 5.5 v package mn = so8n (150 mils width) mc = ufdfpn8 (mlp8) dw = tssop8 device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c option t = tape and reel packing capacitance /2 = 27.5 pf docid022712 rev 7 135/141 M24LR64E-R part numbering table 131. ordering an d marking information reference package ordering code first line marking initial revision 0xf actual revision 0xe and below M24LR64E-R tssop08 M24LR64E-Rdw6t/2 464eu 4feub mlp M24LR64E-Rmc6t/2 464e 4feb so8n M24LR64E-Rmn6t/2 24l64er 24lferb anticollision algorithm (informative) M24LR64E-R 136/141 docid022712 rev 7 appendix a anticollision algorithm (informative) the following pseudocode descri bes how anticollision could be implemented on the vcd, using recursivity. a.1 algorithm for pulsed slots function push (mask, address); pushes on private stack function pop (mask, address); pops from private stack function pulse_next_pause; generates a power pulse function store(M24LR64E-R_uid); stores M24LR64E-R_uid function poll_loop (sub_address_size as integer) pop (mask, address) mask = address & mask; generates new mask ; send the request mode = anticollision send_request (request_cmd, mode, mask length, mask value) for sub_address = 0 to (2^sub_address_size - 1) pulse_next_pause if no_collision_is_detected ; M24LR64E-R is inventoried then store (M24LR64E-R_uid) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ; if some collisions have been detected and then ; not yet processed, the function calls itself poll_loop (sub_address_size); recursively to process the last stored collision endif end poll_loop main_cycle: mask = null address = null push (mask, address) poll_loop(sub_address_size) end_main_cycle docid022712 rev 7 137/141 M24LR64E-R crc (informative) appendix b crc (informative) b.1 crc error detection method the cyclic redundancy check (crc) is calculat ed on all data contained in a message, from the start of the flags through to the end of data. the crc is used from vcd to m24lr64e- r and from M24LR64E-R to vcd. to add extra protection against shifting errors , a further transformation on the calculated crc is made. the one?s complement of the ca lculated crc is the value attached to the message for transmission. to check received messages, the two crc bytes are often also included in the re- calculation, for ease of use. in this case, the expected va lue for the generated crc is the residue f0b8h. b.2 crc calculation example this example in c langu age illustrates one method of calculating th e crc on a given set of bytes comprising a message. c-example to calculate or check t he crc16 according to iso/iec 13239 #define polynomial0x8408// x^16 + x^12 + x^5 + 1 #define preset_value0xffff #define check_value0xf0b8 #define number_of_bytes4// example: 4 data bytes #define calc_crc1 #define check_crc0 void main() { unsigned int current_crc_value; unsigned char array_of_databytes[number_of_bytes + 2] = {1, 2, 3, 4, 0x91, 0x39}; int number_of_databytes = number_of_bytes; int calculate_or_check_crc; int i, j; calculate_or_check_crc = calc_crc; // calculate_or_check_crc = check_crc;// this could be an other example if (calculate_or_check_crc == calc_crc) { number_of_databytes = number_of_bytes; table 132. crc definition crc type length polynomial direction preset residue iso/iec 13239 16 bits x 16 + x 12 + x 5 + 1 = 8408h backward ffffh f0b8h crc (informative) M24LR64E-R 138/141 docid022712 rev 7 } else // check crc { number_of_databytes = number_of_bytes + 2; } current_crc_value = preset_value; for (i = 0; i < number_of_databytes; i++) { current_crc_value = current_crc_value ^ ((unsigned int)array_of_databytes[i]); for (j = 0; j < 8; j++) { if (current_crc_value & 0x0001) { current_crc_value = (current_crc_value >> 1) ^ polynomial; } else { current_crc_value = (current_crc_value >> 1); } } } if (calculate_or_check_crc == calc_crc) { current_crc_value = ~current_crc_value; printf ("generated crc is 0x%04x\n", current_crc_value); // current_crc_value is now ready to be appended to the data stream // (first lsbyte, then msbyte) } else // check crc { if (current_crc_value == check_value) { printf ("checked crc is ok (0x%04x)\n", current_crc_value); } else { printf ("checked crc is not ok (0x%04x)\n", current_crc_value); } } } docid022712 rev 7 139/141 M24LR64E-R application family identifier (afi) (informative) appendix c application family identifier (afi) (informative) the afi (application family identifier) represents the type of application targeted by the vcd and is used to extract from all the m24lr64e -rs present only the one meeting the required application criteria. it is programmed by the M24LR64E-R issuer (the purchaser of the M24LR64E-R). once locked, it cannot be modified. the most significant nibble of the afi is used to code one specific or all application families, as defined in table 133 . the least significant nibble of the afi is us ed to code one specific or all application subfamilies. subfamily codes diff erent from 0 ar e proprietary. table 133. afi coding (1) 1. x = '1' to 'f', y = '1' to 'f' afi most significant nibble afi least significant nibble meaning viccs respond from examples / note ?0? ?0? all families and subfamilies no applicative preselection ?x? '0 all subfamilies of family x wide applicative preselection 'x '?y? only the yth s ubfamily of family x - ?0? ?y? proprietary subfamily y only - ?1 '?0?, ?y? transport mass transit, bus, airline,... '2 '?0?, ?y? financial iep, banking, retail,... '3 '?0?, ?y? identificat ion access control,... '4 '?0?, ?y? telecommunication public telephony, gsm,... ?5? ?0?, ?y? medical - '6 '?0?, ?y? multimedia internet services.... '7 '?0?, ?y? gaming - 8 '?0?, ?y? data storage portable files,... '9 '?0?, ?y? item management - 'a '?0?, ?y? express parcels - 'b '?0?, ?y? postal services - 'c '?0?, ?y? airline bags - 'd '?0?, ?y? rfu - 'e '?0?, ?y? rfu - ?f? ?0?, ?y? rfu - revision history M24LR64E-R 140/141 docid022712 rev 7 revision history table 134. document revision history date revision changes 12-apr-2012 1 initial release. 08-jun-2012 2 updated section 7.1: rf communication and energy harvesting on page 42 and figure 49: M24LR64E-R state transition diagram on page 66 . updated clock pulse width values in table 123: i2c ac characteristics on page 123 . 19-jun-2012 3 updated notes for figure 49: M24LR64E-R state transition diagram on page 66 . 21-feb-2013 4 ? number of sectors updated in section 3 . ? updated section 4.2 . ? updated figure 6: memory sector organization . ? m24lr64e changed into m24lr64x in figure 52: m24lr64e rf- busy management following inventory command , figure 56: m24lr64e rf-busy management following write command and figure 57: m24lr64e rf-wip management following write command . ? updated table 15: control register , table 17: system parameter sector , table 118: absolute maximum ratings , table 122: i2c dc characteristics and table 124: rf characteristics . 07-mar-2013 5 added table 131: ordering and marking information . 12-jun-2013 6 added ?dynamic nfc/rfid tag ic? to the title, section 1: description , and the m24lr definition in table 130: ordering information scheme for packaged devices . updated v esd and note 5 in table 118: absolute maximum ratings . removed mb package from figure 88: ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package outline . 21-nov-2014 7 updated figure 1: logic diagram , figure 14: 100% modulation waveform and figure 15: 10% modulation waveform . updated footnote 4 in table 123: i2c ac characteristics . added note on engineering samples marking in section 31: part numbering . docid022712 rev 7 141/141 M24LR64E-R 141 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved |
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